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set active_design seg_drive //×¢Ò⣺ÏàµÈÓÚÒ»¸öºê¶¨Ò壬ÓÃactive_design´úÌæseg_drive read_verilog {encode_seg.v number_mod.v scan.v seg_drive.v} //read_fileÒ²¿ÉÒÔ£¬Ëü¿ÉÒÔ¶Á¶àÖÖ¸ñʽÎļþ£¬°üÀ¨.db

#analyze -format verilog {encode_seg.v number_mod.v scan.v seg_drive.v}

#elaborate $active_design //×¢ÒâÕâÀïÊÇ$active_design

current_design $active_design //½«¶¥²ãÉèÖóɵ±Ç°Éè¼Æ link

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set_svf ./mapped/svf/$active_design.svf //û²é

###############################################1 # Define the Design Environment

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set_operating_conditions slow //É趨һ¸ö¿âµÄ»·¾³£¬¿âÄÚ°üº¬Ê¹ÓÃζȡ¢µçѹ¡¢µçÂ·ÌØÕ÷Ïß

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2£©set_wire_load_model ¨Cname model_name ¨Clib_name library ¨Cmax ¨Cmin//É趨Ï߸ºÔØÄ£ÐÍ

set_wire_load_model -name tsmc090_wl40 -library slow //±íʾʹÓÿâslowÀïµÄ

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Èç¹ûûÓÐ wire_load_model£¬¿ÉÒÔ½« auto_wire_load_selection ²ÎÊýÉèÖÃΪ true,Ôò DC ×Ô¶¯¸ù¾Ý×ÛºÏÖ®ºóµÄÃæ»ýÀ´Ñ¡ÔñÒ»¸öͳ¼ÆµÄÏ߸ºÔØÄ£ÐÍÓÃÓÚ¹À¼ÆÁ¬ÏßÑÓ³Ù¡£ set auto_wire_load_selection true

set_wire_load_mode enclosed //¿çÄ£¿éÏ߸ºÔØÄ£Ê½Ñ¡Ôñ

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Êä³ö¶Ë£ºÉèÖÃset_load

ÓÉÓÚÍⲿµç·µÄ¸ºÔؽ«»áÓ°Ïìµ½½Óµ½¶Ë¿ÚÉϵ¥Ôªµç·µÄÑÓ³Ù£¨ÕâÀïÉèÖõÄÊǵçÈÝÖµ£©£¬Òò´Ë£¬ ÐèÒª¶Ô¶Ë¿ÚµÄ´ø¸ºÔØÄÜÁ¦×öÏÞÖÆ¡£ÎªÁ˱ȽϾ«È·µØ¼ÆËãÊä³öµç·µÄÑÓ³Ù£¬ DCÐèÒªÖªµÀÊä³öµç·Çý¶¯µÄËùÓиºÔØ¡£²Î¿´p144

²Î¿´@@Design Compiler User Guide 2010.03 p44

È磺set_load [load_of ssc_core_slow/buf1a2/A] [all_outputs]

set_load [expr 4*[load_of DICE_DELAY_DFF_RN_slow/DICE_DELAY_DFF_RN/D]] [all_outputs]

ÊäÈë¶Ë£ºÉèÖÃset_driving_cell

set_driving_cell -lib_cell DICE_DELAY_DFF_RN -pin Q ¨Clibrary DICE_DELAY_DFF_RN_slow [all_inputs]

set_drive 0 [list clk_62_5M rst_n] //²Î¼ûDesign Compiler User Guide 2010.03.pdf 144Ò³

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¿ÚµÄ¹ý¶Éʱ¼ä£¨transition time£© ¡£set_drive ʹÓÃÒ»¸öÈ·¶¨µÄÖµÀ´¹À¼ÆÊäÈë¶ËµÄÊäÈëµç×裬

´Ó¶øµÃµ½ÊäÈë¶Ë¿ÚµÄÑÓ³Ù£»¶ø set_driving_cell ÊǼٶ¨Ò»¸öʵ¼ÊµÄÇý¶¯µ¥ÔªÀ´¹À¼ÆÊäÈëµÄ transtion time£ºTime = arrive_time + drive*net_load +connect_delay dc_shell> current_design top_level_design dc_shell> set_drive 1.5 {I1 I2}

dc_shell> current_design sub_design2 //×¢ÒâÇл»µ±Ç°Éè¼Æ dc_shell> set_driving_cell -lib_cell IV {I3}

dc_shell> set_driving_cell -lib_cell AN2 -pin Z -from_pin B {I4}

################################### # Design constraint

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