input ENABLE; input RESET;
output [9:0]COUNT; output FULL;
reg [9:0]COUNT_I; reg FULL_I;
always @ (posedge CLK or posedge RESET) begin
if (RESET) // asynchronous reset begin
COUNT_I = 10'b0000000000; FULL_I = 1'b0; end
else // active clock edge begin
if (ENABLE) begin if (COUNT_I == 10'b1111111111) FULL_I = 1'b1; else
COUNT_I = COUNT_I + 1; end end end
assign COUNT = COUNT_I; assign FULL = FULL_I;
endmodule
¸½2 ÓÐÏÞ״̬»úµÄVerilog´úÂë
// a simple state machine
module stm(clk, in, reset, out); input clk, in, reset; output [3:0] out;
reg [3:0] out; reg [1:0] state;
parameter s0=0, s1=1, s2=2, s3=3;
always @(state) begin
case (state) s0:
out = 4'b0000; s1:
out = 4'b0001; s2:
out = 4'b0010; s3:
out = 4'b0100; default:
out = 4'b0000; endcase end
always @(posedge clk or posedge reset) begin
if (reset)
state = s0; else
case (state) s0:
state = s1; s1:
if (in)
state = s0; else
state = s2; s2:
state = s3; s3:
state = s0; endcase end
endmodule
// end of state machine
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