解(2)：用VHDL设计产生01001011001序列 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY S_generator IS
PORT(CLK,CLR: IN STD_LOGIC; --工作时钟/复位信号 S_out: OUT STD_LOGIC);--序列输出位 END S_generator;
ARCHITECTURE behav OF S_generator IS
SIGNAL D: STD_LOGIC_VECTOR(10 DOWNTO 0);--11位循环移位寄存器 BEGIN
PROCESS(CLK,CLR) BEGIN
IF CLK'EVENT AND CLK='1' THEN --时钟到来时，逐位左移循环输出序列位 IF CLR='1' THEN D<=\复位操作，产生11位待输出序列 ELSE
D(10 DOWNTO 1)<=D(9 DOWNTO 0); D(0)<=D(10); S_out<=D(10); END IF; END IF; END PROCESS; END behav;
解(3：)用原理图设计且可预置数的11位序列
8-7 将例8-11(欲设计4选1三态总线)中的四个IF语句分别用四个并列进程语句表达出来。
--8-7 修改【例8-11】(欲设计4选1三态总线)，用4个进程设计4选1通道三态总线(8位)电路 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS
port(input3,input2,input1,input0 :
IN STD_LOGIC_VECTOR(7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY tristate2 ;
ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN
COM3: PROCESS(enable,input3) BEGIN
IF enable=\ END PROCESS;
COM2: PROCESS(enable,input2) BEGIN
IF enable=\ END PROCESS;
COM1: PROCESS(enable,input1) BEGIN
IF enable=\ END PROCESS;
COM0: PROCESS(enable,input0) BEGIN
IF enable=\ END PROCESS;
END ARCHITECTURE multiple_drivers;
10 习 题
10-1 举二例说明，有哪些常用时序电路是状态机比较典型的特殊形式，并说明它们属于什么类型的状态机(编码类型、时序类型和结构类型)。（提示：二进制计数器、“00000001”左循环移位寄存器）
解：1）二进制计数器、循环移位寄存器。
2）二进制计数器：Moore型状态机；顺序编码；状态编码直接输出。 3）“00000001”左循环移位寄存器：Moore型状态机；一位热码；状态编码直接输出。
--(1)计数器：Moore型状态机；顺序编码；状态编码直接输出。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC); END COUNT;
ARCHITECTURE behav OF COUNT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15); type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(3 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --时序组合主控进程，次态转换 IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s8; WHEN s8 => cs<=s9; WHEN s9 => cs<=s10; WHEN s10=> cs<=s11; WHEN s11=> cs<=s12; WHEN s12=> cs<=s13; WHEN s13=> cs<=s14; WHEN s14=> cs<=s15; WHEN s15=> cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF;
IF cs=s15 then COUT<='1'; else COUT<='0'; END IF; END PROCESS;
Q<=val_arr_STATE(cs); END behav;
--(2)\左循环移位寄存器：Moore型状态机；一位热码；状态编码直接输出。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LEFT_SHIFT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Cy: OUT STD_LOGIC); END LEFT_SHIFT;
ARCHITECTURE behav OF LEFT_SHIFT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7);
type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(7 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --时序组合主控进程，次态转换 IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF; END PROCESS;
Q<=val_arr_STATE(cs); Cy<=val_arr_STATE(cs)(7); END behav;
10-2 修改例10-1，将其主控组合进程分解为两个进程，一个负责状态转换，另一个负责输出控制信号。
--10-2 修改例10-1，将其主控组合进程分解为两个进程，一个负责状态转换，另一个负责输出控制信号。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS
PORT(clk,reset : IN STD_LOGIC;--主控时序进程时钟驱动和复位信号