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3-1 ˵Ã÷¶Ë¿ÚģʽINOUTºÍBUFFERÓкÎÒìͬµã¡£P60 INOUT : ¾ßÓÐÈý̬¿ØÖƵÄË«Ïò´«ËÍ¶Ë¿Ú BUFFER: ¾ßÓÐÊä³ö·´À¡µÄµ¥Ïò¶«ºþ³ö¿Ú¡£

3-2 »­³öÓëÒÔÏÂʵÌåÃèÊö¶ÔÓ¦µÄÔ­Àíͼ·ûºÅÔª¼þ: ENTITY buf3s IS --ʵÌå1:Èý̬»º³åÆ÷ PORT(input:IN STD_LOGIC; --ÊäÈë¶Ë enable:IN STD_LOGIC; --ʹÄÜ¶Ë output:OUT STD_LOGIC); --Êä³ö¶Ë END buf3s ;

buf3s input output enable ENTITY mux21 IS --ʵÌå2: 2Ñ¡1¶à·ѡÔñÆ÷ PORT(in0, in1,sel: IN STD_LOGIC; output:OUT STD_LOGIC);

mux21 in0 output in1 sel 3-3 ÊÔ·Ö±ðÓÃIF_THENÓï¾äºÍCASEÓï¾äµÄ±í´ï·½Ê½Ð´³ö´Ëµç·µÄVHDL³ÌÐò,Ñ¡Ôñ¿ØÖÆÐźÅs1ºÍs0µÄÊý¾ÝÀàÐÍΪSTD_LOGIC_VECTOR;µ±s1=¡¯0¡¯,s0=¡¯0¡¯£»s1=¡¯0¡¯,s0=¡¯1¡¯£»s1=¡¯1¡¯,s0=¡¯0¡¯ºÍs1=¡¯1¡¯,s0=¡¯1¡¯Ê±,·Ö±ðÖ´ÐÐy<=a¡¢y<=b¡¢y<=c¡¢y<=d¡£ --½â1£ºÓÃIF_THENÓï¾äʵÏÖ4Ñ¡1¶à·ѡÔñÆ÷ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS

PORT (a,b,c,d: IN STD_LOGIC; s0: IN STD_LOGIC; s1: IN STD_LOGIC; y: OUT STD_LOGIC);

END ENTITY mux41;

ARCHITECTURE if_mux41 OF mux41 IS

SIGNAL s0s1 : STD_LOGIC_VECTOR(1 DOWNTO 0);--¶¨Òå±ê×¼Âß¼­Î»Ê¸Á¿Êý¾Ý BEGIN

s0s1<=s1&s0; --s1Ïಢs0,¼´s1Óës0²¢ÖòÙ×÷ PROCESS(s0s1,a,b,c,d) BEGIN

IF s0s1 = \ THEN y <= a; ELSIF s0s1 = \ THEN y <= b; ELSIF s0s1 = \ THEN y <= c; ELSE y <= d; END IF;

END PROCESS;

END ARCHITECTURE if_mux41;

--½â2£ºÓÃCASEÓï¾äʵÏÖ4Ñ¡1¶à·ѡÔñÆ÷ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41 IS

PORT (a,b,c,d: IN STD_LOGIC; s0: IN STD_LOGIC; s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41;

ARCHITECTURE case_mux41 OF mux41 IS

SIGNAL s0s1 : STD_LOGIC_VECTOR(1 DOWNTO 0);--¶¨Òå±ê×¼Âß¼­Î»Ê¸Á¿Êý¾ÝÀàÐÍ BEGIN

s0s1<=s1&s0; --s1Ïಢs0,¼´s1Óës0²¢ÖòÙ×÷ PROCESS(s0s1,a,b,c,d) BEGIN

CASE s0s1 IS --ÀàËÆÓÚÕæÖµ±íµÄcaseÓï¾ä WHEN \ => y <= a; WHEN \ => y <= b; WHEN \ => y <= c; WHEN \ => y <= d; WHEN OTHERS =>NULL ; END CASE; END PROCESS;

END ARCHITECTURE case_mux41;

3-4 ¸ø³ö1λȫ¼õÆ÷µÄVHDLÃèÊö£»×îÖÕʵÏÖ8λȫ¼õÆ÷¡£ÒªÇó:

1)Ê×ÏÈÉè¼Æ1λ°ë¼õÆ÷,È»ºóÓÃÀý»¯Óï¾ä½«ËüÃÇÁ¬½ÓÆðÀ´,ͼ4-20ÖÐh_suberÊÇ°ë¼õÆ÷,diffÊÇ

Êä³ö²î(diff=x-y),s_outÊǽèλÊä³ö(s_out=1,x

xin yin

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b

diff_out

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--½â(1.1)£ºÊµÏÖ1λ°ë¼õÆ÷h_suber(diff=x-y£»s_out=1,x

PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber;

ARCHITECTURE hs1 OF h_suber IS BEGIN

Diff <= x XOR (NOT y); s_out <= (NOT x) AND y;

END ARCHITECTURE hs1;

--½â(1.2)£º²ÉÓÃÀý»¯ÊµÏÖͼ4-20µÄ1λȫ¼õÆ÷

LIBRARY IEEE; --1λ¶þ½øÖÆÈ«¼õÆ÷˳²ãÉè¼ÆÃèÊö USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS

PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END ENTITY f_suber;

ARCHITECTURE fs1 OF f_suber IS

COMPONENT h_suber --µ÷Óðë¼õÆ÷ÉùÃ÷Óï¾ä PORT(x, y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END COMPONENT;

SIGNAL a,b,c: STD_LOGIC; --¶¨Òå1¸öÐźÅ×÷ΪÄÚ²¿µÄÁ¬½ÓÏß¡£ BEGIN

u1: h_suber PORT MAP(x=>xin,y=>yin, diff=>a, s_out=>b); u2: h_suber PORT MAP(x=>a, y=>sub_in, diff=>diff_out,s_out=>c); sub_out <= c OR b;

END ARCHITECTURE fs1;

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x7 y7 a6 x1 y1 xin sub_out yin u7 sub_in diff_out ¡­¡­¡­¡­¡­¡­. ¡­¡­¡­¡­¡­¡­. xin sub_out yin u1 sub_in diff_out xin sub_out yin u0 sub_in diff_out ´®ÐнèλµÄ8λ¼õ·¨Æ÷

a1 sout diff7

a0 diff1 diff0

x0 y0 sin

--½â(2)£º²ÉÓÃÀý»¯·½·¨£¬ÒÔ1λȫ¼õÆ÷Ϊ»ù±¾Ó²¼þ£»ÊµÏÖ´®ÐнèλµÄ8λ¼õ·¨Æ÷(ÉÏͼËùʾ)¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber_8 IS

PORT(x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC; y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_LOGIC; diff0,diff1,diff2,diff3: OUT STD_LOGIC; diff4,diff5,diff6,diff7,sout: OUT STD_LOGIC); END ENTITY suber_8;

ARCHITECTURE s8 OF suber_8 IS

COMPONENT f_suber --µ÷ÓÃÈ«¼õÆ÷ÉùÃ÷Óï¾ä PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END COMPONENT;

SIGNAL a0,a1,a2,a3,a4,a5,a6: STD_LOGIC; --¶¨Òå1¸öÐźÅ×÷ΪÄÚ²¿µÄÁ¬½ÓÏß¡£ BEGIN

u0:f_suber PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0); u1:f_suber PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1); u2:f_suber PORT MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2); u3:f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3); u4:f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4); u5:f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5); u6:f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6); u7:f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout); END ARCHITECTURE s8;

3-5 ÓÃVHDLÉè¼ÆÒ»¸ö3-8ÒëÂëÆ÷£¬ÒªÇó·Ö±ðÓÃ(Ìõ¼þ)¸³ÖµÓï¾ä¡¢caseÓï¾ä¡¢if elseÓï¾ä»òÒÆλ²Ù×÷·ûÀ´Íê³É¡£±È½ÏÕâ4ÖÖ·½Ê½ÖУ¬ÄÄÒ»ÖÖ×î½ÚÊ¡Âß¼­×ÊÔ´¡£ ½â£¨1£©£ºÌõ¼þ¸³ÖµÓï¾ä

--3-5 3µ½8ÒëÂëÆ÷Éè¼Æ(Ìõ¼þ¸³ÖµÓï¾äʵÏÖ)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --ΪʹÓÃÀàÐÍת»»º¯Êý£¬´ò¿ª´Ë³ÌÐò°ü¡£ ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

WITH CONV_INTEGER(DIN) SELECT DOUT<=\ \ \ \ \ \ \ \

UNAFFECTED WHEN OTHERS; END behave; ½â£¨2£©£ºcaseÓï¾ä

--3-5 3µ½8ÒëÂëÆ÷Éè¼Æ(caseÓï¾äʵÏÖ) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --ΪʹÓÃÀàÐÍת»»º¯Êý£¬´ò¿ª´Ë³ÌÐò°ü¡£ ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

PROCESS (DIN) BEGIN

CASE CONV_INTEGER(DIN) IS WHEN 0 => DOUT<=\ WHEN 1 => DOUT<=\ WHEN 2 => DOUT<=\ WHEN 3 => DOUT<=\ WHEN 4 => DOUT<=\ WHEN 5 => DOUT<=\ WHEN 6 => DOUT<=\ WHEN 7 => DOUT<=\ WHEN OTHERS => NULL; END CASE;

END PROCESS; END behave; ½â£¨3£©£ºif_elseÓï¾ä

--3-5 3µ½8ÒëÂëÆ÷Éè¼Æ(if_elseÓï¾äʵÏÖ) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --ΪʹÓÃÀàÐÍת»»º¯Êý£¬´ò¿ª´Ë³ÌÐò°ü¡£ ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

PROCESS (DIN) BEGIN

IF CONV_INTEGER(DIN)=0 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=1 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=2 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=3 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=4 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=5 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=6 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=7 THEN DOUT<=\ END IF;

END PROCESS; END behave; ½â£¨4£©£ºÒÆλ²Ù×÷·û

--3-5 3µ½8ÒëÂëÆ÷Éè¼Æ(ÒÆλ²Ù×÷ʵÏÖ) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --ΪʹÓÃÀàÐÍת»»º¯Êý£¬´ò¿ª´Ë³ÌÐò°ü¡£ ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

DOUT<=\±»ÒÆλ²¿·ÖÊdz£Êý END behave;

3-6 Éè¼ÆÒ»¸ö±È½Ïµç·£¬µ±ÊäÈëµÄ8421BCDÂë´óÓÚ5ʱÊä³ö1£¬·ñÔòÊä³ö0¡£ --½â£º3-6 Éè¼ÆÒ»¸ö±È½Ïµç·£¬µ±ÊäÈëµÄ8421BCDÂë´óÓÚ5ʱÊä³ö1£¬·ñÔòÊä³ö0¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY g_5_cmp IS

PORT( d_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --ÊäÈëÊý¾Ý

cmp_out : OUT STD_LOGIC); --±È½ÏÊä³ö(1:ÊäÈëÊý¾Ý>5) END g_5_cmp;

ARCHITECTURE BHV OF g_5_cmp IS BEGIN

PROCESS(d_in) BEGIN

IF(d_in>\

cmp_out<='1'; --ÊäÈëÊý¾Ý´óÓÚ5£¬±È½ÏÊä³ö1¡£ else

cmp_out<='0'; --ÊäÈëÊý¾ÝСÓÚµÈÓÚ5£¬±È½ÏÊä³ö0¡£ END IF;

END PROCESS; END BHV;

3-7 ÀûÓÃifÓï¾äÉè¼ÆÒ»¸öÈ«¼ÓÆ÷¡£ --3-7 ÀûÓÃifÓï¾äÉè¼ÆÒ»¸öÈ«¼ÓÆ÷

LIBRARY IEEE; --1λ¶þ½øÖÆÈ«¼ÓÆ÷¶¥²ãÉè¼ÆÃèÊö USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY f_adder IS

PORT (ain,bin,cin : IN STD_LOGIC; cout,sum : OUT STD_LOGIC ); END ENTITY f_adder;

ARCHITECTURE fd1 OF f_adder IS BEGIN

PROCESS (ain,bin,cin) BEGIN

IF ain='1' XOR bin='1' XOR cin='1' THEN sum<='1'; ELSE sum<='0'; END IF;

IF (ain='1' AND bin='1')OR(ain='1' AND cin='1')OR(bin='1' AND cin='1')OR(ain='1' AND bin='1' AND cin='1')

THEN cout<='1'; ELSE cout<='0'; END IF;

END PROCESS;

END ARCHITECTURE fd1;

3-8 Éè¼ÆÒ»¸öÇó²¹ÂëµÄ³ÌÐò£¬ÊäÈëÊý¾ÝÊÇÒ»¸öÓзûºÅµÄ8λ¶þ½øÖÆÊý¡£ --½â£º3-8 Éè¼ÆÒ»¸öÇó²¹ÂëµÄ³ÌÐò£¬ÊäÈëÊý¾ÝÊÇÒ»¸öÓзûºÅµÄ8λ¶þ½øÖÆÊý¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY org_patch IS

PORT( org_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--Ô­ÂëÊäÈë patch_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--²¹ÂëÊä³ö

END org_patch;

ARCHITECTURE BHV OF org_patch IS BEGIN

PROCESS(org_data) BEGIN

IF(org_data(7)='0') THEN

patch_data<=org_data; --org_data>=0£¬²¹Âë=Ô­Âë¡£ else

patch_data<=org_data(7)&(not org_data(6 DOWNTO 0))+1;--org_data<0£¬²¹Âë=|Ô­Âë|È¡·´+1¡£ END IF;

END PROCESS; END BHV;

3-9 Éè¼ÆÒ»¸ö¸ñÀ×ÂëÖÁ¶þ½øÖÆÊýµÄת»»Æ÷¡£ --3-9 Éè¼ÆÒ»¸ö¸ñÀ×ÂëÖÁ¶þ½øÖÆÊýµÄת»»Æ÷¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --ΪʹÓÃÀàÐÍת»»º¯Êý£¬´ò¿ª´Ë³ÌÐò°ü¡£ ENTITY grayTObinary IS

port( DIN: IN STD_LOGIC_VECTOR(3 DOWNTO 0); DOUT: OUT BIT_VECTOR(3 DOWNTO 0)); END grayTObinary;

ARCHITECTURE behave OF grayTObinary IS BEGIN

PROCESS (DIN) BEGIN

CASE DIN IS

WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL;

END CASE; END PROCESS; END behave;

3-10 ÀûÓÃifÓï¾äÉè¼ÆÒ»¸ö3λ¶þ½øÖÆÊýA[2..0]¡¢B[2..0]µÄ±È½ÏÆ÷µç·¡£¶ÔÓڱȽÏ(AB)¡¢(A=B)µÄ½á¹û·Ö±ð¸ø³öÊä³öÐźÅLT=1¡¢GT=1¡¢EQ=1¡£

--3-10 ÀûÓÃifÓï¾äÉè¼ÆÒ»¸ö3λ¶þ½øÖÆÊýA[2..0]¡¢B[2..0]µÄ±È½ÏÆ÷µç·¡£

--¶ÔÓڱȽÏ(AB)¡¢(A=B)µÄ½á¹û·Ö±ð¸ø³öÊä³öÐźÅLT=1¡¢GT=1¡¢EQ=1¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS

PORT( A,B: IN STD_LOGIC_VECTOR(2 DOWNTO 0); --Á½¸ö3λÊäÈë LT: OUT STD_LOGIC; --СÓÚÊä³ö GT: OUT STD_LOGIC; --´óÓÚÊä³ö EQ: OUT STD_LOGIC); --µÈÓÚÊä³ö END ENTITY COMP;

ARCHITECTURE ONE OF COMP IS BEGIN

PROCESS(A,B) BEGIN

IF (AB) THEN GT<='1';ELSE GT<='0';END IF; IF (A=B) THEN EQ<='1';ELSE EQ<='0';END IF; END PROCESS;

-- LT <= (AB); --´óÓÚ -- EQ <= (A=B); --µÈÓÚ END ARCHITECTURE ONE;

3-11 ÀûÓÃ8¸öÈ«¼ÓÆ÷£¬¿ÉÒÔ¹¹³ÉÒ»¸ö8λ¼Ó·¨Æ÷¡£ÀûÓÃÑ­»·Óï¾äÀ´ÊµÏÖÕâÏîÉè¼Æ¡£²¢ÒÔ´ËÏîÉè¼ÆΪÀý£¬Ê¹ÓÃGENERIC²ÎÊý´«µÝµÄ¹¦ÄÜ£¬Éè¼ÆÒ»¸ö32λ¼Ó·¨Æ÷¡£ --3-11 ÀûÓÃGENERIC²ÎÊýºÍÑ­»·Óï¾ä½«8¸öÈ«¼ÓÆ÷¹¹³É³É8λ¼Ó·¨Æ÷ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY ADDER8B IS

GENERIC(S: INTEGER:=8); --¶¨Òå²ÎÊýSΪÕûÊýÀàÐÍ£¬ÇÒµÈÓÚ4 PORT(A,B: IN STD_LOGIC_VECTOR(S-1 DOWNTO 0); CIN: IN STD_LOGIC;

SUM: OUT STD_LOGIC_VECTOR(S-1 DOWNTO 0); COUT: OUT STD_LOGIC); END ENTITY ADDER8B;

ARCHITECTURE ONE OF ADDER8B IS BEGIN

PROCESS(A,B,CIN)

VARIABLE S1: STD_LOGIC_VECTOR(S-1 DOWNTO 0);

VARIABLE C1: STD_LOGIC;--_VECTOR(S DOWNTO 0); BEGIN C1:=CIN; --C1(0):=CIN;

FOR i IN 1 TO S LOOP

IF A(i-1)='1' XOR B(i-1)='1' XOR C1='1' THEN S1(i-1):='1'; ELSE S1(i-1):='0'; END IF;

IF (A(i-1)='1' AND B(i-1)='1')OR(A(i-1)='1' AND C1='1')OR(B(i-1)='1' AND C1='1')OR(A(i-1)='1' AND B(i-1)='1' AND C1='1') THEN C1:='1'; ELSE C1:='0'; END IF; END LOOP;

SUM<=S1;COUT<=C1; END PROCESS;

END ARCHITECTURE ONE;

3-12 Éè¼ÆÒ»¸ö2λBCDÂë¼õ·¨Æ÷¡£×¢Òâ¿ÉÒÔÀûÓÃBCDÂë¼Ó·¨Æ÷À´ÊµÏÖ¡£ÒòΪ¼õÈ¥Ò»¸ö¶þ½øÖÆÊý£¬µÈÓÚ¼ÓÉÏÕâ¸öÊýµÄ²¹Âë¡£Ö»ÊÇÐèҪעÒ⣬×÷Ϊʮ½øÖƵÄBCDÂëµÄ²¹Âë»ñÈ¡·½Ê½ÓëÆÕͨ¶þ½øÖÆÊýÉÔÓв»Í¬¡£ÎÒÃÇÖªµÀ¶þ½øÖÆÊýµÄ²¹ÂëÊÇÕâ¸öÊýµÄÈ¡·´¼Ó1¡£¼ÙÉèÓÐÒ»¸ö4λ¶þ½øÖÆÊýÊÇ0011£¬ÆäÈ¡²¹Êµ¼ÊÉÏÊÇÓÃ1111¼õÈ¥0011£¬ÔÙ¼ÓÉÏl¡£ÏàÀàËÆ£¬ÒÔ4λ¶þ½øÖƱí´ïµÄBCDÂëµÄÈ¡²¹ÔòÊÇÓÃ9(1001)¼õÈ¥Õâ¸öÊýÔÙ¼ÓÉÏ1¡£

--3-12 Éè¼Æ2λBCDÂë¼õ·¨Æ÷(ÀûÓüõÈ¥ÊýµÈÓÚ¼ÓÉϸÃÊý²¹Âë·½·¨) (a-b=a+[-b]²¹Âë) LIBRARY IEEE; --´ýÀý»¯Ôª¼þ USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_arith.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; ENTITY SUB2BCD IS

PORT(a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); diff: out STD_LOGIC_VECTOR(7 DOWNTO 0); sout: OUT STD_LOGIC); END SUB2BCD;

ARCHITECTURE behave OF SUB2BCD IS BEGIN

PROCESS(a,b)

VARIABLE cc: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN

IF a

IF cc(3 DOWNTO 0) > \ IF cc(7 DOWNTO 4) > \

cc:=a+cc;

IF cc(3 DOWNTO 0) > \ IF cc(7 DOWNTO 4) > \

IF a

cc:=\

IF cc(3 DOWNTO 0) > \ IF cc(7 DOWNTO 4) > \ END IF;

diff<=cc;

END PROCESS; END behave;

3-13 Éè¼ÆÒ»¸ö4λ³Ë·¨Æ÷£¬Îª´ËÊ×ÏÈÉè¼ÆÒ»¸ö¼Ó·¨Æ÷£¬ÓÃÀý»¯Óï¾äµ÷ÓÃÕâ¸ö¼Ó·¨Æ÷£¬ÓÃÒÆλÏà¼ÓµÄ·½Ê½Íê³É³Ë·¨¡£²¢ÒÔ´ËÏîÉè¼ÆΪ»ù´¡£¬Ê¹ÓÃGENERIC²ÎÊý´«µÝµÄ¹¦ÄÜ£¬Éè¼ÆÒ»¸ö16λ³Ë·¨Æ÷¡£

--3-13 4λÒÆλÏà¼ÓÐͳ˷¨Æ÷Éè¼Æ(Àý»¯µ÷Óüӷ¨Æ÷) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MULT4B IS

GENERIC( S: INTEGER:=4); --¶¨Òå²ÎÊýSΪÕûÊýÀàÐÍ£¬ÇÒµÈÓÚ4 PORT( R: OUT STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); A,B: IN STD_LOGIC_VECTOR(S-1 DOWNTO 0)); END ENTITY MULT4B;

ARCHITECTURE ONE OF MULT4B IS COMPONENT addern IS

PORT(a,b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END COMPONENT;

SIGNAL A0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0);

SIGNAL RR3,RR2,RR1,RR0,ZZ1,ZZ0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); BEGIN

A0<=CONV_STD_LOGIC_VECTOR(0,S) & A; PROCESS(A,B) BEGIN

IF(B(0)='1')THEN RR0<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 0);ELSE RR0<=(OTHERS=>'0');END IF; IF(B(1)='1')THEN RR1<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 1);ELSE RR1<=(OTHERS=>'0');END IF; IF(B(2)='1')THEN RR2<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 2);ELSE RR2<=(OTHERS=>'0');END IF; IF(B(3)='1')THEN RR3<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 3);ELSE RR3<=(OTHERS=>'0');END IF;

END PROCESS;

u0: addern PORT MAP(a=>RR0,b=>RR1,result=>ZZ0);

u1: addern PORT MAP(a=>ZZ0,b=>RR2,result=>ZZ1); u2: addern PORT MAP(a=>ZZ1,b=>RR3,result=>R); END ARCHITECTURE ONE;

--3-13a 16λ³Ë·¨Æ÷(ͨ¹ýµ×²ã3-13_MULTSBºÍ¶¥²ãGENERIC²ÎÊýºÍ´«µÝÀý»¯Óï¾äʵÏÖ)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY MULT16B IS

PORT(D1,D2: IN STD_LOGIC_VECTOR(15 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END;

ARCHITECTURE BHV OF MULT16B IS

COMPONENT MULTSB --MULTS8Ä£¿éµÄµ÷ÓÃÉùÃ÷

GENERIC(S: integer); --ÕÕ³­MULTSBʵÌåÖйØÓÚ²ÎÊý¡°¶Ë¿Ú¡±¶¨ÒåµÄÓï¾ä PORT(R: OUT std_logic_vector(2*S-1 DOWNTO 0); A,B: IN std_logic_vector(S-1 DOWNTO 0)); END COMPONENT ; BEGIN

u1: MULTSB GENERIC MAP(S=>16) PORT MAP(R=>Q,A=>D1,B=>D2); END;

3-14 ÓÃÑ­»·Óï¾äÉè¼ÆÒ»¸ö7ÈËͶƱ±í¾öÆ÷¡£

--½â£º3-14 ÓÃÑ­»·Óï¾äÉè¼ÆÒ»¸ö7ÈËͶƱ±í¾öÆ÷£¬¼°Ò»¸ö4λ4Êä³ö×î´óÊýÖµ¼ì²âµç·¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vote_7 IS

PORT( DIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);--7λ±í¾öÊäÈë(1:ͬÒ⣬0:²»Í¬Òâ)

G_4: OUT STD_LOGIC; --³¬¹ý°ëÊýָʾ

CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));--±í¾ö½á¹ûͳ¼ÆÊý END vote_7;

ARCHITECTURE BHV OF vote_7 IS BEGIN

PROCESS(DIN)

VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN

Q:=\

FOR n IN 0 TO 6 LOOP -- nÊÇLOOPµÄÑ­»·±äÁ¿ IF(DIN(n)='1') THEN Q:=Q+1; END IF; END LOOP; CNTH<=Q;

IF Q>=4 THEN G_4<='1'; ELSE G_4<='0'; END IF; END PROCESS; END BHV;

3-15 Éè¼ÆÒ»¸ö4λ4ÊäÈë×î´óÊýÖµ¼ì²âµç·¡£

--3-15 Éè¼ÆÒ»¸ö4λ4ÊäÈë×î´óÊýÖµ¼ì²âµç·¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MAXDATA IS

PORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0); MAXOUT: OUT STD_LOGIC); END ENTITY MAXDATA;

ARCHITECTURE ONE OF MAXDATA IS BEGIN

PROCESS(A) BEGIN

IF A=\ END PROCESS;

END ARCHITECTURE ONE;

3-16 Éè¼ÆVHDL³ÌÐò£¬ÊµÏÖÁ½¸ö8λ¶þ½øÖÆÊýÏà¼Ó£¬È»ºó½«ºÍ×óÒÆ»òÓÒÒÆ4룬²¢·Ö±ð½«ÒÆλºóµÄÖµ´æÈë±äÁ¿AAºÍBBÖС£

--3-16 Éè¼ÆVHDL³ÌÐò£¬ÊµÏÖÁ½¸ö8λ¶þ½øÖÆÊýÏà¼Ó£¬È»ºó½«ºÍ×óÒÆ»òÓÒÒÆ4룬²¢·Ö±ð½«ÒÆλºóµÄÖµ´æÈë±äÁ¿AºÍBÖС£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY ADDER8B IS

GENERIC(S: INTEGER:=8); --¶¨Òå²ÎÊýSΪÕûÊýÀàÐÍ£¬ÇÒµÈÓÚ4 PORT(A,B: IN STD_LOGIC_VECTOR(S-1 DOWNTO 0); CIN: IN STD_LOGIC;

SUM: OUT STD_LOGIC_VECTOR(S-1 DOWNTO 0); COUT: OUT STD_LOGIC;

AA,BB: OUT STD_LOGIC_VECTOR(S-1+4 DOWNTO 0)); END ENTITY ADDER8B;

ARCHITECTURE ONE OF ADDER8B IS BEGIN

PROCESS(A,B,CIN)

VARIABLE S1: STD_LOGIC_VECTOR(S-1 DOWNTO 0); VARIABLE C1: STD_LOGIC;

VARIABLE AB: STD_LOGIC_VECTOR(S-1+4 DOWNTO 0); BEGIN C1:=CIN;

FOR i IN 1 TO S LOOP

IF A(i-1)='1' XOR B(i-1)='1' XOR C1='1' THEN S1(i-1):='1'; ELSE S1(i-1):='0'; END IF;

IF (A(i-1)='1' AND B(i-1)='1')OR(A(i-1)='1' AND C1='1')OR(B(i-1)='1' AND

C1='1')OR(A(i-1)='1' AND B(i-1)='1' AND C1='1') THEN C1:='1'; ELSE C1:='0'; END IF; END LOOP;

SUM<=S1;COUT<=C1;

AA<=TO_STDLOGICVECTOR(TO_BITVECTOR(\ BB<=TO_STDLOGICVECTOR(TO_BITVECTOR(\ END PROCESS;

END ARCHITECTURE ONE; 3-17 ¾ÙÀý˵Ã÷GENERIC˵Ã÷Óï¾ä£¨ÔÚʵÌ嶨ÒåÓï¾äÖж¨ÒåÀàÊô³£Êý£©ºÍGENERICÓ³ÉäÓï¾ä£¨ÔÚÀý»¯Óï¾äÖн«ÀàÊô³£Êý¸³ÓèÐÂÖµ£©ÓкÎÓô¦¡£P82

3-18 ±í´ïʽC<=A+BÖУ¬A¡¢BºÍCµÄÊý¾ÝÀàÐͶ¼ÊÇSTD_LOGIC_VECTOR£¬ÊÇ·ñÄÜÖ±½Ó½øÐмӷ¨ÔËËã?˵Ã÷Ô­ÒòºÍ½â¾ö·½·¨¡£ÄÜ£¨µÚÒ»ÖÖ½«A¡¢Bת»»³ÉÕûÐÍÊýÏà¼Ó½á¹ûÔÙת»»³ÉÂß¼­Î»Ê¸ºóËÍC P89£»µÚ¶þÖÖʹÓÃUSE IEEE.SDT_LOGIC_UNSIGNED.ALLÓï¾ä´ò¿ªÖØÔØÔËËã·û³ÌÐò°ü¡£ P70£¬P130£©

3-19 VHDLÖÐÓÐÄÄÈýÖÖÊý¾Ý¶ÔÏó?Ïêϸ˵Ã÷ËüÃǵŦÄÜÌصãÒÔ¼°Ê¹Ó÷½·¨£¬¾ÙÀý˵Ã÷Êý¾Ý¶ÔÏóÓëÊý¾ÝÀàÐ͵ĹØϵ¡£Ðźţ¬±äÁ¿£¬³£Á¿ P71

3-20 ÄÜ°ÑÈÎÒâÒ»ÖÖ½øÖƵÄÖµÏòÒ»ÕûÊýÀàÐ͵ÄÊý¾Ý¶ÔÏó¸³ÖµÂð?Èç¹ûÄÜ£¬ÔõÑù×ö? ÄÜ£¨ÈôA,B,C,DÊÇÐźÅÕûÊýÀàÐÍ£¬A<=16#df#;B<=8#23#;C<=2#01#;D<=10£©P83 3-21 »Ø´ðÓйØBITºÍBOOLEANÊý¾ÝÀàÐ͵ÄÎÊÌ⣺P59

(1)½âÊÍBIT(¡®0¡¯£»¡®1¡¯)ºÍBOOLEAN(¡°TRUE¡±£¬¡°FALSE¡±)ÀàÐ͵ÄÇø±ð¡£ (2)¶ÔÓÚÂß¼­²Ù×÷ӦʹÓÃÄÄÖÖÀàÐÍ?BIT (3)¹Øϵ²Ù×÷µÄ½á¹ûΪÄÄÖÖÀàÐÍ? BOOLEAN

(4)IFÓï¾ä²âÊԵıí´ïʽÊÇÄÄÖÖÀàÐÍ? BOOLEAN

3-22 ÓÃÁ½ÖÖ·½·¨Éè¼Æ8λ±È½ÏÆ÷£¬±È½ÏÆ÷µÄÊäÈëÊÇÁ½¸ö´ý±È½ÏµÄ8λÊýA=[A7..A0]ºÍB=[B7..80]£¬Êä³öÊÇD¡¢E¡¢F¡£µ±A=BʱD=1£»µ±A>BʱE=1£»µ±A

--3-22 ±È½ÏÆ÷µÄÊäÈëÊÇÁ½¸ö´ý±È½ÏµÄ8λÊýA=[A7..A0]ºÍB=[B7..80]£¬Êä³öÊÇEQ¡¢GT¡¢F¡£µ±A=BʱEQ=1£»µ±A>BʱGT=1£»µ±A

--µÚÒ»ÖÖÉè¼Æ·½°¸Êdz£¹æµÄ±È½ÏÆ÷Éè¼Æ·½·¨£¬¼´Ö±½ÓÀûÓùØϵ²Ù×÷·û½øÐбà³ÌÉè¼Æ¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS

PORT( A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Á½¸ö3λÊäÈë LT: OUT STD_LOGIC; --СÓÚÊä³ö GT: OUT STD_LOGIC; --´óÓÚÊä³ö EQ: OUT STD_LOGIC); --µÈÓÚÊä³ö END ENTITY COMP;

ARCHITECTURE ONE OF COMP IS BEGIN

PROCESS(A,B) BEGIN

IF (AB) THEN GT<='1';ELSE GT<='0';END IF; IF (A=B) THEN EQ<='1';ELSE EQ<='0';END IF; END PROCESS;

END ARCHITECTURE ONE;

--3-22 ±È½ÏÆ÷µÄÊäÈëÊÇÁ½¸ö´ý±È½ÏµÄ8λÊýA=[A7..A0]ºÍB=[B7..80]£¬Êä³öÊÇEQ¡¢GT¡¢F¡£µ±A=BʱEQ=1£»µ±A>BʱGT=1£»µ±A

--µÚ¶þÖÖÉè¼Æ·½°¸ÊÇÀûÓüõ·¨Æ÷À´Íê³É£¬Í¨¹ý¼õ·¨ÔËËãºóµÄ·ûºÅºÍ½á¹ûÀ´ÅбðÁ½¸ö±»±È½ÏÖµµÄ´óС¡£

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS

PORT( A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Á½¸ö3λÊäÈë LT: OUT STD_LOGIC; --СÓÚÊä³ö GT: OUT STD_LOGIC; --´óÓÚÊä³ö EQ: OUT STD_LOGIC); --µÈÓÚÊä³ö END ENTITY COMP;

ARCHITECTURE ONE OF COMP IS

SIGNAL C: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL D,E,F,G: INTEGER RANGE 255 DOWNTO 0; BEGIN C<=A-B;

D<=10;

E<=16#D9#; F<=8#72#;

G<=2#11010010#; PROCESS(A,B) BEGIN

IF (C(7)='1') THEN LT<='1';ELSE LT<='0';END IF; IF (C=0) THEN EQ<='1'; ELSE EQ<='0';

IF(C(7)='0')THEN GT<='1';ELSE GT<='0';END IF; END IF;

END PROCESS;

END ARCHITECTURE ONE;

3-23 ¸ù¾Ýͼ3-19£¬ÓÃÁ½ÖÖ²»Í¬ÃèÊö·½Ê½Éè¼ÆÒ»4Ñ¡1¶à·ѡÔñÆ÷¡£ÔÚÉè¼ÆÖÐÐèÒªÌåÏִ˵ç·ÓÉÈý¸ö2Ñ¡l¶à·ѡÔñÆ÷¹¹³É¡£½â1:²ã´ÎÀý»¯£»½â2:µ¥²ã3½ø³Ì¡£

--½â1£º²ã´ÎÀý»¯¡£µ×²ãÔª¼þmux21a.vhd³ÌÐòÈçÏ£º LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS

PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS BEGIN

PROCESS(a,b,s) BEGIN

IF s='0' THEN y<=a; ELSE y<=b; END IF;

END PROCESS;

END ARCHITECTURE one;

--½â1£º²ã´ÎÀý»¯¡£¶¥²ãmux41b.vhd³ÌÐòÈçÏ£º LIBRARY ieee;

USE ieee.std_logic_1164.all; ENTITY mux41b IS

port(X0,X1,X2,X3: IN STD_LOGIC; S0,S1: IN STD_LOGIC; OUTY: OUT STD_LOGIC); END mux41b;

ARCHITECTURE bdf_type OF mux41b IS component mux21a

PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); end component;

signal N0,N1: STD_LOGIC; BEGIN

u1: mux21a PORT MAP(a=>X0,b=>X1,s=>S0,y=>N0); u2: mux21a PORT MAP(a=>X2,b=>X3,s=>S0,y=>N1); u3: mux21a PORT MAP(a=>N0,b=>N1,s=>S1,y=>OUTY); END;

--½â2£ºµ¥²ã½á¹¹mux41a.vhd³ÌÐòÈçÏ£º LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS

PORT(x1,x2,x3,x4,s0,s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41a;

ARCHITECTURE one OF mux41a IS signal N0,N1: STD_LOGIC; BEGIN

com1: PROCESS(x1,x2,s0) BEGIN

IF s0='0' THEN N0<=x1; ELSE

N0<=x2; END IF;

END PROCESS;

com2: PROCESS(x3,x4,s0) BEGIN

IF s0='0' THEN N1<=x3; ELSE

N1<=x4; END IF;

END PROCESS;

com3: PROCESS(N0,N1,s1) BEGIN

IF s1='0' THEN y<=N0; ELSE y<=N1; END IF;

END PROCESS;

END ARCHITECTURE one;

4 Ï° Ìâ

4-1 ¹éÄÉÀûÓÃQuartus II½øÐÐVHDLÎı¾ÊäÈëÉè¼ÆµÄÁ÷³Ì£º´ÓÎļþÊäÈëÒ»Ö±µ½Ó²¼þ¹¦ÄܲâÊÔ¡£P96~P110

´ð£º1 ½¨Á¢¹¤×÷¿âÎļþ¼ÐºÍ±à¼­Éè¼ÆÎļþ£»2 ´´½¨¹¤³Ì£»3 ±àÒëÇ°ÉèÖã»4 È«³Ì±àÒ룻5 ʱÐò·ÂÕ棻6 Òý½ÅËø¶¨£»7 ÅäÖÃÎļþÏÂÔØ£»8 ´ò¿ªSignalTap II±à¼­´°¿Ú£»9 µ÷ÈëSignalTap IIµÄ´ý²âÐźţ»10 SignalTap II²ÎÊýÉèÖã»11 SignalTap II²ÎÊýÉèÖÃÎļþ´æÅÌ£»12 ´øÓÐSignalTap II²âÊÔÐÅÏ¢µÄ±àÒëÏÂÔØ£»13 Æô¶¯SignalTap II½øÐвÉÑùÓë·ÖÎö£»14 SignalTap IIµÄÆäËûÉèÖúͿØÖÆ·½·¨¡£

4-2 ²Î¿¼Quartus IIµÄHelp£¬Ïêϸ˵Ã÷Assignments²Ëµ¥ÖÐSettings¶Ô»°¿òµÄ¹¦ÄÜ¡£ £¨1£©ËµÃ÷ÆäÖеÄTiming Requirements & QptionsµÄ¹¦ÄÜ¡¢Ê¹Ó÷½·¨ºÍ¼ì²â;¾¶¡£ £¨2£©ËµÃ÷ÆäÖеÄCompilation ProcessµÄ¹¦ÄܺÍʹÓ÷½·¨¡£

£¨3£©ËµÃ÷Analysis & Synthesis SettingµÄ¹¦ÄܺÍʹÓ÷½·¨£¬ÒÔ¼°ÆäÖеÄSynthesis Netlist OptimizationµÄ¹¦ÄܺÍʹÓ÷½·¨¡£

(1)˵Ã÷ÆäÖеÄTiming Requirements&QptionsµÄ¹¦ÄÜ¡¢ËûÓ÷½·¨ºÍ¼ì²â;¾­¡£ Specifying Timing Requirements and Options (Classic Timing Analyzer)

You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins.

When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals.

You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings.

3. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values

under Delay requirements.

4. To specify project-wide minimum delay requirements, specify options under

Minimum delay requirements.

5. Under Clock Settings, select Default required fmax.

6. In the Default required fmax box, type the value of the required fMAX and select a time

unit from the list.

7. If you want to specify options for cutting or reporting certain types of timing paths

globally, enabling recovery/removal analysis, enabling clock latency, and reporting unconstrained timing paths, follow these steps: 8. Click OK.

To specify clock settings:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings. 3. Under Clock Settings, click Individual Clocks. 4. Click New.

5. In the New Clock Settings dialog box, type a name for the new clock settings in the

Clock settings name box.

6. To assign the clock settings to a clock signal in the design, type a clock node name in

the Applies to node box, or click Browse... to select a node name using the Node Finder.

7. If you want to specify timing requirements for an absolute clock, follow these steps: 8. If you have already specified timing requirements for an absolute clock, and you want

to specify timing requirements for a derived clock, follow these steps: 9. In the New Clock Settings dialog box, click OK. 10. In the Individual Clocks dialog box, click OK. 11. In the Settings dialog box, click OK. To specify individual timing requirements:

1. On the Assignments menu, click Assignment Editor.

2. In the Category bar, select Timing to indicate the category of assignment you wish to

make.

3. In the spreadsheet, select the To cell and perform one of the following steps:

? Type a node name and/or wildcard that identifies the destination node(s) you

want to assign.

? Double-click the To cell and click Node Finder to use the Node Finder to enter

a node name.

Double-click the To cell, click the arrow that appears on the right side of the cell, and click Select Assignment Group to enter an existing assignment group name.

4. To specify an assignment source, repeat step 3 to specify the source name in the

From cell.

5. In the spreadsheet, double-click the Assignment Name cell and select the timing

assignment you wish to make.

6. For assignments that require a value, double-click the Value cell and type or select

the appropriate assignment value.

To specify timing analysis reporting restrictions: 1. On the Assignments menu, click Settings.

2. In the Category list, double-click Timing Analysis Settings. 3. Click Timing Analyzer Reporting.

4. To specify the range of timing analysis information reported, specify one or more

options in the Timing Analyzer Reporting page. 5. Click OK.

(2)˵Ã÷ÆäÖеÄCompilation ProcessµÄ¹¦ÄܺÍʹÓ÷½·¨¡£ Compilation Process Settings Page (Settings Dialog Box)

Allows you to direct the Compiler to use smart compilation, save synthesis results for the current design's top-level entity, disable the OpenCore Plus hardware evaluation feature, or export version-compatible database files. You can also control the amount of disk space used for compilation.

Use Smart compilation:

Preserve fewer node names to save disk space: Run Assembler during compilation:

Save a node-level netlist of the entire design into a persistent source file: Export version-compatible database: Display entity name for node name:

Disable OpenCore Plus hardware evaluation feature: (3)˵Ã÷Analysis&Synthesis SettingµÄ¹¦ÄܺÍʹÓ÷½·¨£¬ÒÔ¼°ÆäÖеÄSynthesis Netlist OptimizationµÄ¹¦ÄܺÍʹÓ÷½·¨¡£

Analysis & Synthesis Settings Page (Settings Dialog Box) Allows you to specify options for logic synthesis. Create debugging nodes for IP cores: More Settings: Other options: Message Level: Advanced:

Synthesis Netlist Optimizations Page (Settings Dialog Box)

Specifies the following options for optimizing netlists during synthesis: Perform WYSIWYG primitive resynthesis: Perform gate-level register retiming:

Allow register retiming to trade off Tsu/Tco with Fmax:

?

4-3 ¸ÅÊöAssignments²Ëµ¥ÖÐAssignment EditorµÄ¹¦ÄÜ£¬¾ÙÀý˵Ã÷¡£

About the Assignment Editor

User Interface and Functionality: Customizing the User Interface: Pin Information:

LogicLock Assignments:

Assignment Validation and Output: Integration with the Pin Planner:

4-4 È«³Ì±àÒëÖ÷Òª°üÀ¨Äļ¸¸ö¹¦ÄÜÄ£¿é?ÕâЩ¹¦ÄÜÄ£¿é¸÷ÓÐʲô×÷ÓÃ?P99~101

4-5 ÓÐÄÄÈýÖÖÒý½ÅËø¶¨µÄ·½·¨?Ïêϸ˵Ã÷ÕâÈýÖÖ·½·¨µÄʹÓÃÁ÷³ÌºÍ×¢ÒâÊÂÏ²¢ËµÃ÷ËüÃǸ÷×ÔµÄÌص㡣Ìáʾ£¬µÚÈýÖÖ·½·¨ÊÇÑ¡ÔñAssignmentsÖеÄPins¶Ô»°¿ò£¬½øÐÐÒý½ÅÉèÖá£P103~105 4-6 Ïêϸ˵Ã÷ͨ¹ýJTAG¿Ú¶ÔFPGAµÄÅäÖÃFlash EPCSÆ÷¼þµÄ¼ä½Ó±à³Ì·½·¨ºÍÁ÷³Ì¡£P106~107

4-7 ¶ÔµÚ3ÕµÄÏ°Ìâ3-13ºÍÏ°Ìâ3-14µÄÉè¼Æ½á¹û£¬Óñ¾Õ½éÉܵķ½·¨£¬·Ö±ðÔÚQuartus¢òÉϽøÐзÂÕ棬ÑéÖ¤ÆäÕýÈ·ÐÔ£»È»ºóÔÚEP3C55оƬÖнøÐÐÓ²¼þ²âÊÔºÍÑéÖ¤¡£

--3-13 4λÒÆλÏà¼ÓÐͳ˷¨Æ÷Éè¼Æ(Àý»¯µ÷Óüӷ¨Æ÷) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MULT4B IS

GENERIC( S: INTEGER:=4); --¶¨Òå²ÎÊýSΪÕûÊýÀàÐÍ£¬ÇÒµÈÓÚ4 PORT( R: OUT STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); A,B: IN STD_LOGIC_VECTOR(S-1 DOWNTO 0)); END ENTITY MULT4B;

ARCHITECTURE ONE OF MULT4B IS COMPONENT addern IS

PORT(a,b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END COMPONENT;

SIGNAL A0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0);

SIGNAL RR3,RR2,RR1,RR0,ZZ1,ZZ0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); BEGIN

A0<=CONV_STD_LOGIC_VECTOR(0,S) & A; PROCESS(A,B) BEGIN

IF(B(0)='1')THEN RR0<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 0);ELSE RR0<=(OTHERS=>'0');END IF; IF(B(1)='1')THEN RR1<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 1);ELSE RR1<=(OTHERS=>'0');END IF; IF(B(2)='1')THEN RR2<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 2);ELSE RR2<=(OTHERS=>'0');END IF; IF(B(3)='1')THEN RR3<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 3);ELSE RR3<=(OTHERS=>'0');END IF; END PROCESS;

u0: addern PORT MAP(a=>RR0,b=>RR1,result=>ZZ0); u1: addern PORT MAP(a=>ZZ0,b=>RR2,result=>ZZ1); u2: addern PORT MAP(a=>ZZ1,b=>RR3,result=>R); END ARCHITECTURE ONE;

--½â£º3-14 ÓÃÑ­»·Óï¾äÉè¼ÆÒ»¸ö7ÈËͶƱ±í¾öÆ÷£¬¼°Ò»¸ö4λ4Êä³ö×î´óÊýÖµ¼ì²âµç·¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vote_7 IS

PORT( DIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);--7λ±í¾öÊäÈë(1:ͬÒ⣬0:²»Í¬Òâ) G_4: OUT STD_LOGIC; --³¬¹ý°ëÊýָʾ CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));--±í¾ö½á¹ûͳ¼ÆÊý END vote_7;

ARCHITECTURE BHV OF vote_7 IS BEGIN

PROCESS(DIN)

VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN Q:=\

FOR n IN 0 TO 6 LOOP -- nÊÇLOOPµÄÑ­»·±äÁ¿ IF(DIN(n)='1') THEN Q:=Q+1; END IF; END LOOP; CNTH<=Q;

IF Q>=4 THEN G_4<='1'; ELSE G_4<='0'; END IF; END PROCESS; END BHV;

4-8 Èç¹û¶ÔÓÚÒ»¸öÉè¼ÆÏîÄ¿£¬ÈçÈ«¼ÓÆ÷½øÐÐÈ«³Ì±àÒ룬¼ÙÉèÒѽ«ÐźŶ˿ÚcoutºÍsum·Ö±ðËø¶¨ÓÚÒý½ÅDlºÍK22£¬±àÒëºó·¢ÏÖQuartus II¸ø³ö±àÒ뱨´í£º¡°Can't place multiple pins

assigned to pin Location Pin D1(»òK22)¡±£¬ÊÔÎÊ£¬ÎÊÌâ³öÔÚÄÄÀï?ÈçºÎ½â¾ö?P99

Ìáʾ£º¿¼ÂÇ¿ÉÄÜÕâЩÒý½Å¾ßÓÐË«¹¦ÄÜ¡£Ñ¡Ôñͼ4-5Ëùʾ´°¿ÚÖеÄË«Ä¿±ê¶Ë¿ÚÉèÖÃÒ³£¬È罫nCEOÔ­À´µÄ¡°Use as programming pin¡±¸ÄΪ¡°Use as regular I/O¡±¡£ÕâÑù¿ÉÒÔ½«´Ë¶Ë¿ÚÒ²×÷ÆÕͨI/O¿ÚÀ´Óᣠ4-9 ÓÃ74148£¨8-3Ï߰˽øλÓÅÏȱàÂëÆ÷£©ºÍÓë·ÇÃÅʵÏÖ8421BCDÓÅÏȱàÂëÆ÷¡£ÓÃ3Ƭ74139£¨2Ïß-4ÏßÒëÂëÆ÷£©×é³ÉÒ»¸ö5-24ÏßÒëÂëÆ÷¡£

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²¢ËµÃ÷ÕâÒ»¹¦ÄܵÄÌص㼰ÓÅÊÆ¡£P113~114

4-14 ¶ÔÀý3-23ºÍÀý3-24½øÐзÂÕ棬ÑéÖ¤Æ书ÄÜ£¬²¢Ïêϸ˵Ã÷³ÌÐò½á¹¹ºÍ¸÷Óï¾ä¹¦ÄÜ¡£ÊÔÓýø³ÌÓï¾äÍê³ÉÏàͬ¹¦ÄÜ¡£

--½â1£º4-14¡¾Àý3-23¡¿0¡«255·¶Î§ÄÚµÄ×ÔÈ»Êýת»»³É8λ¶þ½øÖÆÊý¡£ LIBRARY IEEE; --Ö÷³ÌÐò£¬Óû§¶¨Òåת»»º¯ÊýÓ¦ÓÃʵÀý USE IEEE.STD_LOGIC_1164.ALL; USE WORK.n_pack.ALL; ENTITY axamp IS

PORT(dat: IN nat; --×¢ÒâÊý¾ÝÀàÐ͵Ķ¨Òå ou: OUT Bit8); --×¢ÒâÊý¾ÝÀàÐ͵Ķ¨Òå END;

ARCHITECTURE bhv OF axamp IS BEGIN

ou<=nat_to_Bit8(dat); END; --½â2£º4-14¡¾Àý3-24¡¿×ÔÈ»Êýת»»³É¶þ½øÖÆÊýµÄ³ÌÐò°ü(²»ÄܶÀÁ¢×ۺϷÂÕæ¡£±»¡¾Àý3-23¡¿´ò¿ªÊ¹ÓÃ)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; PACKAGE n_pack IS

SUBTYPE nat IS Integer range 0 to 255;--¶¨ÒåÒ»¸öIntegerµÄ×ÓÀàÐÍ TYPE Bit8 IS array(7 downto 0)OF std_logic;--¶¨ÒåÒ»¸öÊý¾ÝÀàÐÍ FUNCTION nat_to_Bit8(s:nat)RETURN Bit8; END n_pack;

PACKAGE BODY n_pack IS

FUNCTION nat_to_Bit8(s:nat)RETURN Bit8 IS VARIABLE Din: Integer range 255 downto 0; VARIABLE Rut: Bit8;

VARIABLE Rig: Integer:=2**7; BEGIN Din:=S;

FOR I in 7 downto 0 LOOP

IF Din/Rig > 0 THEN Rut(i):='1';Din:=Din-Rig; ELSE Rut(i):='0'; END IF; Rig:=Rig/2; END LOOP; RETURN Rut; END nat_to_Bit8; END n_pack;

5 Ï° Ìâ

5-1 ÔÚVHDLÉè¼ÆÖУ¬¸øʱÐòµç·Çå0(¸´Î»)ÓÐÁ½ÖÖ²»Í¬·½·¨£¬ËüÃÇÊÇʲô?ÈçºÎʵÏÖ?ͬ²½ºÍÒì²½¸´Î»¡£P122~124

--½â1£º5-1¡¾Àý5-4¡¿º¬Òì²½¸´Î»ºÍʱÖÓʹÄܵÄD´¥·¢Æ÷

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS

PORT(CLK,RST,EN,D: IN STD_LOGIC; Q: OUT STD_LOGIC); END;

ARCHITECTURE bhv OF DFF1 IS

SIGNAL Q1:STD_LOGIC; --ÀàËÆÓÚÔÚоƬÄÚ²¿¶¨ÒåÒ»¸öÊý¾ÝµÄÔÝ´æ½Úµã BEGIN

PROCESS (CLK,Q1,RST,EN) BEGIN

IF RST='1' THEN Q1<='0';

ELSIF CLK'EVENT AND CLK='1' THEN IF EN='1' THEN Q1<=D; END IF; END IF;

END PROCESS;

Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö END bhv;

--½â2£º5-1¡¾5-5¡¿º¬Í¬²½¸´Î»¿ØÖƵÄD´¥·¢Æ÷ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS

PORT(CLK,RST,D: IN STD_LOGIC; Q: OUT STD_LOGIC); END;

ARCHITECTURE bhv OF DFF1 IS

SIGNAL Q1:STD_LOGIC; --ÀàËÆÓÚÔÚоƬÄÚ²¿¶¨ÒåÒ»¸öÊý¾ÝµÄÔÝ´æ½Úµã BEGIN

PROCESS(CLK,Q1,RST) BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF RST='1' THEN Q1<='0';ELSE Q1<=D;END IF; END IF; END PROCESS;

Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö END bhv; 5-2 ¾ÙÀý£¨¡¾Àý5-1¡¿£©ËµÃ÷£¬ÎªÊ²Ã´Ê¹ÓÃÌõ¼þÐðÊö²»ÍêÕûµÄÌõ¼þ¾äÄܵ¼Ö²úÉúʱÐòÄ£¿éµÄ×ۺϽá¹û¡£

ÓÉÓÚ²»ÍêÕûÌõ¼þ¾ä¾ßÓжÔÊä³öÐźŲ»×ö´¦Àí(¼´±£³ÖÏÖ×´)µÄÐÐΪ£¬¶øµ¼ÖÂʱÐòµç·×ۺϽá¹û¡£(P121)

--½â£º5-2¡¾Àý5-1¡¿D´¥·¢Æ÷

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS

PORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUT STD_LOGIC); END;

ARCHITECTURE bhv OF DFF1 IS

SIGNAL Q1:STD_LOGIC; --ÀàËÆÓÚÔÚоƬÄÚ²¿¶¨ÒåÒ»¸öÊý¾ÝµÄÔÝ´æ½Úµã BEGIN

PROCESS(CLK,Q1) BEGIN

IF CLK'EVENT AND CLK='1' --ÉÏÉýÑØ´¥·¢Ëø´æ THEN Q1<=D; END IF; END PROCESS;

Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö END bhv;

5-3 Éè¼ÆÒ»¸ö¾ßÓÐͬ²½ÖÃ1£¬Òì²½Çå0µÄD´¥·¢Æ÷¡£ --5-3 Éè¼ÆÒ»¸ö¾ßÓÐͬ²½ÖÃ1£¬Òì²½Çå0µÄD´¥·¢Æ÷¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS

PORT(CLK,RST,SET,D: IN STD_LOGIC; Q: OUT STD_LOGIC); END;

ARCHITECTURE bhv OF DFF1 IS

SIGNAL Q1:STD_LOGIC; --ÀàËÆÓÚÔÚоƬÄÚ²¿¶¨ÒåÒ»¸öÊý¾ÝµÄÔÝ´æ½Úµã BEGIN

PROCESS (CLK,Q1,RST,SET) BEGIN

IF RST='1' THEN Q1<='0';

ELSIF CLK'EVENT AND CLK='1' THEN IF SET='1' THEN Q1<='1'; ELSE Q1<=D; END IF; END IF;

END PROCESS;

Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö END bhv;

5-4 °ÑÀý5-15(Òì²½¸´Î»ºÍͬ²½¼ÓÔØÊ®½øÖƼӷ¨¼ÆÊýÆ÷)¸Äд³ÉÒ»Òì²½Çå0£¬Í¬²½Ê±ÖÓʹÄܺÍÒì²½Êý¾Ý¼ÓÔØÐÍ8λ¶þ½øÖƼӷ¨¼ÆÊýÆ÷¡£

--5-4 Òì²½Çå0£¬Í¬²½Ê±ÖÓʹÄܺÍÒì²½Êý¾Ý¼ÓÔØÐÍ8λ¶þ½øÖƼӷ¨¼ÆÊýÆ÷¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS

PORT(CLK,RST,EN,LOAD : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4λԤÖÃÊý DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--¼ÆÊýÖµÊä³ö COUT : OUT STD_LOGIC); --¼ÆÊý½øλÊä³ö END CNT10;

ARCHITECTURE behav OF CNT10 IS BEGIN

PROCESS(CLK,RST,EN,LOAD)

VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF RST='0' THEN Q:=(OTHERS =>'0'); --¼ÆÊýÆ÷Òì²½¸´Î» ELSIF LOAD='0' THEN Q:=DATA; --ÔÊÐí¼ÓÔØ

ELSIF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ

IF EN='1' THEN --¼ì²âÊÇ·ñÔÊÐí¼ÆÊý»ò¼ÓÔØ£¨Í¬²½Ê¹ÄÜ£© IF Q<9 THEN Q:=Q+1; --ÔÊÐí¼ÆÊý,¼ì²âÊÇ·ñСÓÚ9 ELSE Q:=(OTHERS=>'0'); --´óÓÚµÈÓÚ9ʱ£¬¼ÆÊýÖµÇåÁã END IF; END IF; END IF; IF Q=9 THEN COUT<='1'; --¼ÆÊý´óÓÚ9£¬Êä³ö½øλÐźŠELSE COUT<='0'; END IF;

DOUT<=Q; --½«¼ÆÊýÖµÏò¶Ë¿ÚÊä³ö END PROCESS; END behav;

5-5 ÊÔ¶ÔÏ°Ìâ5-4µÄÉè¼ÆÉÔ×÷Ð޸ģ¬½«Æä½øλÊä³öCOUTÓëÒì²½¼ÓÔØ¿ØÖÆLOADÁ¬ÔÚÒ»Æ𣬹¹³ÉÒ»¸ö×Ô¶¯¼ÓÔØÐÍ16(4)λ¶þ½øÖÆÊý¼ÆÊýÆ÷£¬¼´Ò»¸öl6(4)λ¿É¿ØµÄ·ÖƵÆ÷£¬²¢ËµÃ÷¹¤×÷Ô­Àí¡£ÉèÊäÈëƵÂÊfi=4MHz£¬Êä³öƵÂÊf0=(516.5¡À1)Hz(ÔÊÐíÎó²î¡À0.1Hz)£¬Çó16λ¼ÓÔØÊýÖµ¡£

--5-5 ÊÔ¶ÔÏ°Ìâ5-4µÄÉè¼ÆÉÔ×÷Ð޸ģ¬½«Æä½øλÊä³öCOUTÓëÒì²½¼ÓÔØ¿ØÖÆLOADÁ¬ÔÚÒ»Æ𣬠--¹¹³ÉÒ»¸ö×Ô¶¯¼ÓÔØÐÍ16(4)λ¶þ½øÖÆÊý¼ÆÊýÆ÷£¬¼´Ò»¸öl6(4)λ¿É¿ØµÄ·ÖƵÆ÷£¬²¢ËµÃ÷¹¤×÷Ô­Àí¡£ --ÉèÊäÈëƵÂÊfi=4MHz£¬Êä³öƵÂÊf0=(516.5¡À1)Hz(ÔÊÐíÎó²î¡À0.1Hz)£¬Çó16λ¼ÓÔØÊýÖµ¡£

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS

PORT(CLK,RST,EN : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4λԤÖÃÊý DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--¼ÆÊýÖµÊä³ö COUT : BUFFER STD_LOGIC); --¼ÆÊý½øλÊä³ö END CNT10;

ARCHITECTURE behav OF CNT10 IS BEGIN

PROCESS(CLK,RST,EN,COUT)

VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); --SIGNAL BEGIN

IF RST='0' THEN Q:=(OTHERS =>'0'); --¼ÆÊýÆ÷Òì²½¸´Î» ELSIF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ

IF EN='1' THEN --¼ì²âÊÇ·ñÔÊÐí¼ÆÊý»ò¼ÓÔØ£¨Í¬²½Ê¹ÄÜ£© IF COUT='1' THEN Q:=DATA; --ÔÊÐí¼ÓÔØ ELSE IF Q<9 THEN Q:=Q+1; --ÔÊÐí¼ÆÊý,¼ì²âÊÇ·ñСÓÚ9 ELSE Q:=(OTHERS=>'0'); --´óÓÚµÈÓÚ9ʱ£¬¼ÆÊýÖµÇåÁã END IF; END IF; END IF; END IF; IF Q=9 THEN COUT<='1'; --¼ÆÊý´óÓÚ9£¬Êä³ö½øλÐźŠELSE COUT<='0'; END IF;

DOUT<=Q; --½«¼ÆÊýÖµÏò¶Ë¿ÚÊä³ö END PROCESS; END behav;

5-6 ·Ö±ð¸ø³öRTLͼ(ͼ5-19ºÍͼ5-19)µÄVHDLÃèÊö£¬×¢ÒâÆäÖеÄD´¥·¢Æ÷ºÍËø´æÆ÷µÄ±íÊö¡£

ͼ5-18 RTLͼ1

--½â1£ºÍ¼5-18 RTLͼµÄVHDL³ÌÐòmux21a.vhdµ×²ãÉè¼ÆÃèÊö¡£ -- ÓÃWHEN_ELSEʵÏÖ2Ñ¡1¶à·ѡÔñÆ÷³ÌÐò(mux21a.vhd) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS

PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS BEGIN

y<=a WHEN s='0' ELSE b;

END ARCHITECTURE one;

--½â2£ºÊµÏÖͼ5-18 RTLͼµÄVHDL³ÌÐòDFF6.vhdµ×²ãÉè¼ÆÃèÊö¡£ -- µçƽ´¥·¢DÐÍ´¥·¢Æ÷³ÌÐò(DFF6.vhd) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF6 IS

PORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUT STD_LOGIC); END;

ARCHITECTURE bhv OF DFF6 IS BEGIN

PROCESS(CLK,D) BEGIN

IF CLK='1'

THEN Q<=D; END IF; END PROCESS; END bhv;

-- 5-6 ¸ø³öͼ5-18 RTLͼµÄVHDLÃèÊö¡£

--½â3£ºÊµÏÖͼ5-18 RTLͼµÄVHDL³ÌÐòT5_18.vhd¶¥²ãÉè¼ÆÃèÊö¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY T5_18 IS

PORT(D1,D2,CLK : IN STD_LOGIC; Q : OUT STD_LOGIC); END ENTITY T5_18;

ARCHITECTURE one OF T5_18 IS

COMPONENT mux21a --µ÷ÓÃ2Ñ¡1¶à·ѡÔñÆ÷ÉùÃ÷Óï¾ä PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END COMPONENT;

COMPONENT DFF6 --µ÷ÓõçƽÐÍD´¥·¢Æ÷ÉùÃ÷Óï¾ä PORT(CLK: IN STD_LOGIC; D: IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT;

SIGNAL DD: STD_LOGIC; --¶¨Òå1¸öÐźÅ×÷ΪÄÚ²¿µÄÁ¬½ÓÏß¡£ BEGIN

u1: mux21a PORT MAP(CLK,D2,D1,DD); u2: DFF6 PORT MAP(CLK,DD,Q); END ARCHITECTURE one;

ͼ5-19 RTLͼ2

--½â1£ºÊµÏÖͼ5-19 RTLͼµÄVHDL³ÌÐòmux21a.vhdµ×²ãÉè¼ÆÃèÊö -- ÓÃWHEN_ELSEʵÏÖ2Ñ¡1¶à·ѡÔñÆ÷³ÌÐò(mux21a.vhd) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS

PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS BEGIN

y<=a WHEN s='0' ELSE b; END ARCHITECTURE one;

--½â2£ºÊµÏÖͼ5-19 RTLͼµÄVHDL³ÌÐòDFF_PRE_CLR.vhd¶¥²ãÉè¼ÆÃèÊö -- ´øÔ¤Öá¢ÇåÁãºÍÊä³öʹÄܵÄÉÏÉýÑØD´¥·¢Æ÷³ÌÐò(DFF_PRE_CLR.vhd) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF_PRE_CLR_ENA IS PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END;

ARCHITECTURE bhv OF DFF_PRE_CLR_ENA IS

SIGNAL Q1:STD_LOGIC; --ÀàËÆÓÚÔÚоƬÄÚ²¿¶¨ÒåÒ»¸öÊý¾ÝµÄÔÝ´æ½Úµã BEGIN

PROCESS(CLK,D,Q1,ENA,PRE,CLR) BEGIN

IF CLR='1' THEN Q1<='0'; ELSIF PRE='1' THEN Q1<='1';

ELSIF CLK'EVENT AND CLK='1' AND ENA='1' THEN Q1<=D; END IF;

--IF EN='1' THEN Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö --END IF;

Q<=Q1; --½«ÄÚ²¿µÄÔÝ´æÊý¾ÝÏò¶Ë¿ÚÊä³ö END PROCESS; END bhv;

-- 5-6 ¸ø³öͼ5-19 RTLͼµÄVHDLÃèÊö¡£

--½â3£ºÊµÏÖͼ5-19 RTLͼµÄVHDL³ÌÐòT5_19.vhd¶¥²ãÉè¼ÆÃèÊö LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY T5_19 IS

PORT(RST,D,CLK : IN STD_LOGIC; Q,DOUT : OUT STD_LOGIC); END ENTITY T5_19;

ARCHITECTURE one OF T5_19 IS

COMPONENT DFF_PRE_CLR_ENA --µ÷ÓÃD´¥·¢Æ÷ÉùÃ÷Óï¾ä PORT(CLK : IN STD_LOGIC; D : IN STD_LOGIC; Q :OUT STD_LOGIC; ENA : IN STD_LOGIC; PRE : IN STD_LOGIC; CLR : IN STD_LOGIC); END COMPONENT;

COMPONENT mux21a --µ÷ÓÃD´¥·¢Æ÷ÉùÃ÷Óï¾ä PORT(a,b : IN STD_LOGIC; s : IN STD_LOGIC; y : OUT STD_LOGIC); END COMPONENT;

SIGNAL DD,DDD: STD_LOGIC; --¶¨Òå1¸öÐźÅ×÷ΪÄÚ²¿µÄÁ¬½ÓÏß¡£ BEGIN

u1: mux21a PORT MAP(D,'0',RST,DD); DDD<=D XOR DD;

u2: DFF_PRE_CLR_ENA PORT MAP(CLK,DDD,DOUT,'1','0','0'); u3: DFF_PRE_CLR_ENA PORT MAP(CLK,DD,Q,'1','0','0'); END ARCHITECTURE one;

5-7 ÓÃVHDLÉè¼ÆÒ»¸ö¹¦ÄÜÀàËÆ74LS160(Òì²½¸´Î»ºÍͬ²½Ê¹ÄܼÓÔصÄÊ®½øÖƼӷ¨¼ÆÊýÆ÷)µÄ¼ÆÊýÆ÷¡£

--5-7 ÓÃVHDLÉè¼ÆÒ»¸ö¹¦ÄÜÀàËÆ74LS160(Òì²½¸´Î»ºÍͬ²½Ê¹ÄܼÓÔØ¡¢¼ÆÊýµÄÊ®½øÖƼӷ¨¼ÆÊýÆ÷)µÄ¼ÆÊýÆ÷¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS

PORT(CLK,RST,EN,LOAD : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --4λԤÖÃÊý

DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);--¼ÆÊýÖµÊä³ö COUT : OUT STD_LOGIC); --¼ÆÊý½øλÊä³ö END CNT10;

ARCHITECTURE behav OF CNT10 IS BEGIN

PROCESS(CLK,RST,EN,LOAD)

VARIABLE Q : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

IF RST='0' THEN Q:=(OTHERS =>'0'); --¼ÆÊýÆ÷Òì²½¸´Î» ELSIF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ

IF EN='1' THEN --¼ì²âÊÇ·ñÔÊÐí¼ÆÊý»ò¼ÓÔØ£¨Í¬²½Ê¹ÄÜ£© IF LOAD='0' THEN Q:=DATA; --ÔÊÐí¼ÓÔØ ELSE

IF Q<9 THEN Q:=Q+1; --ÔÊÐí¼ÆÊý,¼ì²âÊÇ·ñСÓÚ9

ELSE Q:=(OTHERS=>'0'); --´óÓÚµÈÓÚ9ʱ£¬¼ÆÊýÖµÇåÁã END IF; END IF; END IF; END IF;

IF Q=9 THEN COUT<='1'; --¼ÆÊý´óÓÚ9£¬Êä³ö½øλÐźŠELSE COUT<='0'; END IF;

DOUT<=Q; --½«¼ÆÊýÖµÏò¶Ë¿ÚÊä³ö END PROCESS; END behav;

5-8 ¸ø³öº¬ÓÐÒì²½Çå0ºÍ¼ÆÊýʹÄܵÄ16λ¶þ½øÖƼӼõ¿É¿Ø¼ÆÊýÆ÷µÄVHDLÃèÊö¡£

--½â£º5-8 ¸ø³öº¬ÓÐÒì²½ÇåÁãºÍ¼ÆÊýʹÄܵÄ16λ¶þ½øÖƼӼõ¿É¿Ø¼ÆÊýÆ÷(´øÔ¤ÖÃÊý)µÄVHDLÃèÊö¡£ -- ÓÃVHDLʵÏÖº¬ÓÐÒì²½ÇåÁãºÍ¼ÆÊýʹÄܵÄ16λ¶þ½øÖƼӼõ¿É¿Ø¼ÆÊýÆ÷¡£

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADD_SUB_LOAD_16 IS

PORT (CLK,RST,ADD_EN,SUB_EN,LOAD : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; CQ : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; COUT : OUT STD_LOGIC);

END ENTITY ADD_SUB_LOAD_16;

ARCHITECTURE A_S_16 OF ADD_SUB_LOAD_16 IS BEGIN

PROCESS(CLK,RST,ADD_EN,SUB_EN,LOAD)

VARIABLE CQI: STD_LOGIC_VECTOR(15 DOWNTO 0); --VARIABLE LS_LOAD : STD_LOGIC; BEGIN

--LS_LOAD:=LOAD;

IF RST = '1' THEN CQI:=(OTHERS => '0');--¼ÆÊýÆ÷Òì²½¸´Î»

ELSIF LOAD = '1' THEN CQI:=DATA; --LS_LOAD:='0'; --¼ÆÊýÆ÷Òì²½¸´Î» ELSIF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ IF ADD_EN='1'THEN --¼ì²âÊÇ·ñÔÊÐí¼ÆÊý(ͬ²½ËûÄÜ)

IF CQI<16#FFFF# THEN CQI:=CQI+1; --ÔÊÐí¼ÆÊý,¼ì²âÊÇ·ñСÓÚ65535 ELSE CQI:=(OTHERS => '0'); --´óÓÚ65535,¼ÆÊýÖµÇåÁã END IF;

IF CQI=16#FFFF# THEN COUT<='1'; --¼ÆÊý´óÓÚ9,Êä³ö½øλÐźŠELSE COUT <= '0'; END IF; END IF;

IF SUB_EN='1'THEN --¼ì²âÊÇ·ñÔÊÐí¼ÆÊý(ͬ²½ËûÄÜ)

IF CQI>0 THEN CQI:=CQI-1; --ÔÊÐí¼ÆÊý,¼ì²âÊÇ·ñСÓÚ65535 ELSE CQI:=(OTHERS => '1'); --´óÓÚ65535,¼ÆÊýÖµÇåÁã END IF;

IF CQI=0 THEN COUT<='1'; --¼ÆÊý´óÓÚ9,Êä³ö½øλÐźŠELSE COUT <= '0'; END IF; END IF; END IF;

CQ<=CQI; --½«¼ÆÊýÖµÏò¶Ë¿ÚÊä³ö END PROCESS;

END ARCHITECTURE A_S_16; 5-9 »ùÓÚÔ­ÀíͼÊäÈ뷽ʽ£¬ÓÃD´¥·¢Æ÷¹¹³É°´Ñ­»·Âë(000->001->011->111->101->100->000)¹æÂɹ¤×÷µÄÁù½øÖÆͬ²½¼ÆÊýÆ÷¡£

5-10 »ùÓÚÔ­ÀíͼÊäÈ뷽ʽ£¬Ó¦ÓÃ4λȫ¼ÓÆ÷(74283)ºÍ74374(8D´¥·¢Æ÷)¹¹³É4λ¶þ½øÖÆ

¼Ó·¨¼ÆÊýÆ÷¡£Èç¹ûʹÓÃ74299£¨8λͨÓÃÒÆλ¼Ä´æÆ÷£©¡¢74373£¨8DËø´æÆ÷£©¡¢D´¥·¢Æ÷ºÍ·ÇÃÅÀ´Íê³ÉÉÏÊö¹¦ÄÜ£¬Ó¦¸ÃÓÐÔõÑùµÄµç·£¿

5-11 (1) (2) »ùÓÚÔ­ÀíͼÊäÈ뷽ʽ£¬ÓÃһƬ74163£¨¿ÉÔ¤ÖÃ4λ¶þ½øÖƼÆÊýÆ÷£©ºÍÁ½Æ¬74138£¨3Ïß-8ÏßÒëÂëÆ÷£©¹¹³ÉÒ»¸ö¾ßÓÐ12·Âö³åÊä³öµÄÊý¾Ý·ÖÅäÆ÷¡£ÒªÇóÔÚÔ­ÀíͼÉϱêÃ÷µÚ1·µ½µÚ12·Êä³öµÄλÖá£Èô¸ÄÓÃһƬ74195£¨4λͨÓÃÒÆλ¼Ä´æÆ÷£©´úÌæÒÔÉϵÄ74163 £¨¿ÉÔ¤ÖÃ4λ¶þ½øÖƼÆÊýÆ÷£©£¬ÊÔÍê³ÉͬÑùµÄÉè¼Æ¡£

5-12 ÓÃͬ²½Ê±Ðòµç·¶Ô´®Ðжþ½øÖÆÊäÈë½øÐÐÆæżУÑ飬ÿ¼ì²â5λÊäÈ룬Êä³öÒ»¸ö½á¹û¡£µ±5λÊäÈëÖÐ1µÄÊýĿΪÆæÊýʱ£¬ÔÚ×îºóһλµÄʱ¿ÌÊä³ö1¡£(ͬ²½¸´Î») (Òì²½¸´Î»)

--½â1(ͬ²½¸´Î»)£º5-12 ÓÃͬ²½Ê±Ðòµç·¶Ô´®Ðжþ½øÖÆÊäÈë½øÐÐÆæżУÑ飬ÿ¼ì²â5λÊäÈ룬Êä³öÒ»¸ö½á¹û¡£ -- µ±5λÊäÈëÖÐ1µÄÊýĿΪÆæÊýʱ£¬ÔÚ×îºóһλµÄʱ¿ÌÊä³ö1¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY odd_even_p_RXD_5 IS

PORT (CLK,RST,S_in: IN STD_LOGIC;--CLK¡¢RST¡¢S_in:ʱÖÓ¡¢¸´Î»¡¢´®ÐÐÊäÈëÊý¾Ý P_out: OUT STD_LOGIC_VECTOR(4 DOWNTO 0);--P_out:²¢ÐÐÊä³öÊý¾Ý o_e_out: OUT STD_LOGIC); --o_e_out:ÆæУÑéÊä³öλ END ENTITY odd_even_p_RXD_5;

ARCHITECTURE one OF odd_even_p_RXD_5 IS BEGIN

PROCESS(CLK,RST)

VARIABLE shift_Q : STD_LOGIC_VECTOR(4 DOWNTO 0);--shift_Q:ÒÆλ¼Ä´æÆ÷ VARIABLE shift_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);--shift_cnt:ÒÆλ¼ÆÊýÆ÷ BEGIN

IF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ

IF RST = '1' THEN shift_cnt:=\ --ÒÆλ¼Ä´æÆ÷ºÍ¼ÆÊýÆ÷¸´Î» ELSE

IF shift_cnt=4 THEN --¼ì²âµ½½ÓÊÕ5λ´®ÐÐÊäÈëÊý¾Ý

shift_cnt:=\ --ÒÆλ¼ÆÊýÆ÷ÇåÁ㣬Ϊ½ÓÊÕÏÂÒ»×éÊý¾Ý×ö×¼±¸¡£ P_out<=shift_Q;--½ÓÊÕÊý¾Ý²¢ÐÐÊä³ö

o_e_out<=shift_Q(4) XOR shift_Q(3) XOR shift_Q(2) XOR shift_Q(1) XOR shift_Q(0);--ÆæУÑéÊä³ö

shift_Q:=S_in & shift_Q(4 DOWNTO 1);--²ÉÑùÒÆλ´®ÐÐÊäÈë ELSE

shift_cnt:=shift_cnt+1;--ÒÆλ¼ÆÊý

shift_Q:=S_in & shift_Q(4 DOWNTO 1);--²ÉÑùÒÆλ´®ÐÐÊäÈë END IF; END IF; END IF; END PROCESS; END ARCHITECTURE one;

--½â2(Òì²½¸´Î»)£º5-12 ÓÃͬ²½Ê±Ðòµç·¶Ô´®Ðжþ½øÖÆÊäÈë½øÐÐÆæżУÑ飬ÿ¼ì²â5λÊäÈ룬Êä³öÒ»¸ö½á¹û¡£ -- µ±5λÊäÈëÖÐ1µÄÊýĿΪÆæÊýʱ£¬ÔÚ×îºóһλµÄʱ¿ÌÊä³ö1¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY odd_even_p_RXD_5 IS

PORT (CLK,RST,S_in: IN STD_LOGIC;--CLK¡¢RST¡¢S_in:ʱÖÓ¡¢¸´Î»¡¢´®ÐÐÊäÈëÊý¾Ý P_out : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);--P_out:²¢ÐÐÊä³öÊý¾Ý o_e_out : OUT STD_LOGIC); --o_e_out:ÆæУÑéÊä³öλ END ENTITY odd_even_p_RXD_5;

ARCHITECTURE one OF odd_even_p_RXD_5 IS BEGIN

PROCESS(CLK,RST)

VARIABLE shift_Q : STD_LOGIC_VECTOR(4 DOWNTO 0);--shift_Q:ÒÆλ¼Ä´æÆ÷ VARIABLE shift_cnt : STD_LOGIC_VECTOR(2 DOWNTO 0);--shift_cnt:ÒÆλ¼ÆÊýÆ÷ BEGIN

IF RST = '1' THEN shift_cnt:=\ --ÒÆλ¼Ä´æÆ÷ºÍ¼ÆÊýÆ÷¸´Î» ELSE

IF CLK'EVENT AND CLK='1' THEN --¼ì²âʱÖÓÉÏÉýÑØ IF shift_cnt=4 THEN --¼ì²âµ½½ÓÊÕ5λ´®ÐÐÊäÈëÊý¾Ý

shift_cnt:=\ --ÒÆλ¼ÆÊýÆ÷ÇåÁ㣬Ϊ½ÓÊÕÏÂÒ»×éÊý¾Ý×ö×¼±¸¡£ P_out<=shift_Q;--½ÓÊÕÊý¾Ý²¢ÐÐÊä³ö

o_e_out<=shift_Q(4) XOR shift_Q(3) XOR shift_Q(2) XOR shift_Q(1) XOR shift_Q(0);--ÆæУÑéÊä³ö

shift_Q:=S_in & shift_Q(4 DOWNTO 1);--²ÉÑùÒÆλ´®ÐÐÊäÈë ELSE

shift_cnt:=shift_cnt+1;--ÒÆλ¼ÆÊý

shift_Q:=S_in & shift_Q(4 DOWNTO 1);--²ÉÑùÒÆλ´®ÐÐÊäÈë END IF; END IF; END IF; END PROCESS; END ARCHITECTURE one;

5-13 »ùÓÚÔ­ÀíͼÊäÈ뷽ʽ£¬ÓÃ7490£¨Ê®½øÖƼÆÊýÆ÷£©Éè¼ÆģΪ872µÄ¼ÆÊýÆ÷£¬ÇÒÊä³ö¸öλ¡¢Ê®Î»¡¢°Ùλ¶¼Ó¦·ûºÏ8421ÂëȨÖØ¡£

5-14 »ùÓÚÔ­ÀíͼÊäÈ뷽ʽ£¬ÓÃ74194¡¢74273¡¢D´¥·¢Æ÷µÈÆ÷¼þ×é³É8λ´®Èë²¢³öµÄת»»µç·£¬ÒªÇóÔÚת»»¹ý³ÌÖÐÊý¾Ý²»±ä£¬Ö»Óе±8λһ×éÊý¾ÝÈ«²¿×ª»»½áÊøºó£¬Êä³ö²Å±ä»¯Ò»´Î¡£(QIIϲ¨ÐηÂÕæ )

6 Ï° Ìâ

6-1 ¹éÄÉÀûÓÃQuartusII½øÐÐVHDLÎı¾ÊäÈëÉè¼ÆµÄÁ÷³Ì£º´ÓÎļþÊäÈëÒ»Ö±µ½SignalTap II²âÊÔ¡£P146~P152

6-2 ÈçºÎΪÉè¼ÆÖеÄSignalTap II¼ÓÈë¶ÀÁ¢²ÉÓÃʱÖÓ£¿ÊÔ¸ø³öÍêÕûµÄ³ÌÐòºÍ¶ÔËüµÄʵ²â½á¹û¡£ P151~P152

ARCHITECTURE ONE OF xxx IS

attribute chip_pin of CLK0£ºsignal is¡±G2 1¡±; --Âß¼­·ÖÎöÒDzÉÑùʱÖÓ 6-3 ¸ù¾Ý6.6.2½ÚµÄÄÚÈÝÍê³ÉQuartus IIÓëSynplifyµÄ½Ó¿Ú£¬²¢Í¨¹ýʵ²â֤ʵÔÚ±àÒëÖÐ Quartus IIµ÷ÓÃÁËSynplify×ÛºÏÆ÷¡£ P159~P161

7 Ï° Ìâ

7-1. Èç¹û²»Ê¹ÓÃMegaWizard Plug-In Manager¹¤¾ß£¬ÈçºÎÔÚ×Ô¼ºµÄÉè¼ÆÖе÷ÓÃLPMÄ£¿é£¿ÒÔ¼ÆÊýÆ÷lpm_counterΪÀý£¬Ð´³öµ÷ÓøÃÄ£¿éµÄ³ÌÐò£¬ÆäÖвÎÊý×Ô¶¨¡£ £¨Ìáʾ£º²Î¿¼Àý7-1£©P171

--7-1 Èç¹û²»Ê¹ÓÃMegawizard Plug_In Manager¹¤¾ß£¬ÈçºÎÔÚ×ÔÒѵÄÉè¼ÆÖе÷ÓÃLPMÄ£¿é? -- ÒÔ¼ÆÊýÆ÷lpm_counterΪÀý£¬Ð´³öµ÷ÓøÃÄ£¿éµÄ³ÌÐò£¬ÆäÖвÎÊý×Ô¶¨¡£ -- ´ð£º1.ÔÚ³ÌÐò¿ªÊ¼²¿·ÖÔö¼Ó´ò¿ª\¿âºÍʹÓÃ\ËùÓгÌÐò°ü¡£ -- ´ð£º2.Ôڽṹ˵Ã÷ÃèÊö²¿·ÖÔö¼Óµ÷ÓÃ\´«µÝ²ÎÊýºÍ¶Ë¿ÚµÄÉêÃ÷¡£

-- ´ð£º3.ÔڽṹÐÐΪÃèÊö²¿·ÖÔö¼Óµ÷ÓÃ\´«µÝ²ÎÊýºÍ¶Ë¿ÚµÄÀý»¯¡£Ê¾ÀýÈçÏ£º -- ´ð£º4.µ÷ÓüÆÊýÆ÷lpm_counter£¨LPMÄ£¿é£©µÄVHDL³ÌÐòÈçÏ£º£¨SINGT_counter.vhd£© LIBRARY ieee;

USE ieee.std_logic_1164.all; LIBRARY lpm;

USE lpm.all;

ENTITY SINGT_counter IS

PORT(clock: IN STD_LOGIC;q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END SINGT_counter;

ARCHITECTURE SYN OF singt_counter IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_counter

GENERIC(lpm_direction : STRING; lpm_port_updown : STRING; lpm_type : STRING; lpm_width : NATURAL);

PORT (clock: IN STD_LOGIC;q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END COMPONENT; BEGIN

q <= sub_wire0(7 DOWNTO 0);

lpm_counter_component : lpm_counter

GENERIC MAP(lpm_direction => \ lpm_type => \ PORT MAP(clock => clock,q => sub_wire0); END SYN;

7-2 ·Ö±ðÒÔͼ7-18(Àý7-1)ºÍÀý7-7(6)µÄ´úÂëÐÎʽÉè¼ÆÁ½¸öÏàͬ²ÎÊýµÄRAM³ÌÐò£¬ËüÃÇÊÇ8(10)λÊý¾ÝÏߺÍ10(8)λµØÖ·Ïß¡£³õʼ»¯ÎļþÊÇmif¸ñʽµÄÕýÏÒ²¨Êý¾ÝÎļþ£¬¼´ºÏ1024¸öµã£¬Ã¿¸öµã8λ¶þ½øÖÆÊýµÄÒ»¸öÖÜÆÚµÄÕýÏÒ²¨²¨ÐΣ¬Éè³õÏàλÊÇ0¡£ÔÚQuartus IIÉϽøÐзÂÕ棬ÑéÖ¤Éè¼ÆµÄÕýÈ·ÐÔ£¬²¢±È½ÏËüÃǵĽṹÌص㡢×ÊÔ´ÀûÓÃÇé¿ö¼°¹¤×÷Ëٶȡ£ --½â1£ºÒÔÀý7-7´úÂëÐÎʽÉè¼ÆRAM(8λÊý¾ÝºÍ10λµØÖ·) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;--´Ë³ÌÐò°üÀ¨º¬×ª»»º¯ÊýCONV_INTEGERlA) USE IEEE.STD_LOGIC_UNSIGNED.ALL;--´Ë³ÌÐò°ü°üº¬Ëã·ûÖØÔغ¯Êý ENTITY RAM10x8 IS

PORT( CLK: IN STD_LOGIC;--¶¨ÒåʱÖÓ

WREN: IN STD_LOGIC;--¶¨ÒåдÔÊÐí¿ØÖÆ

A: IN STD_LOGIC_VECTOR(9 DOWNTO 0);--¶¨ÒåRAMµÄ10λµØÖ·ÊäÈë¶Ë¿Ú DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);--¶¨ÒåRAMµÄ8λÊý¾ÝÊäÈë¶Ë¿Ú Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--¶¨ÒåRAMµÄ8λÊý¾ÝÊä³ö¶Ë¿Ú END;

ARCHITECTURE bhv OF RAM10x8 IS

TYPE G_ARRAY IS ARRAY(0 TO 1024) OF STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL MEM: G_ARRAY;--¶¨ÒåÐźÅMEMµÄÊý¾ÝÀàÐÍΪÓû§Ð¶¨ÒåµÄÀàÐÍG_ARRAY

attribute ram_init_file: string;--¶¨Òå×Ö·û´®ÊôÐԵıêʶ·ûram_init_file¡£ attribute ram_init_file of MEM: --¶¨Òå±êʶ·ûram_init_fileÊÇMEMµÄÊôÐÔ£¬ SIGNAL IS \ --²¢½«×Ö·û´®\³õʼ»¯¸³¸øram_init_file¡£ BEGIN

PROCESS(CLK) BEGIN

IF RISING_EDGE(CLK) THEN

IF WREN='1' THEN --Èç¹ûʱÖÓÓÐÉÏÉýÑسöÏÖ£¬ÇÒдʹÄÜΪ¸ßµçƽ£¬Ôò

MEM(CONV_INTEGER(A))<=DIN;--RAMÊý¾Ý¿ÚµÄÊý¾Ý±»Ð´ÈëÖ¸¶¨µØÖ·µÄµ¥Ôª END IF; END IF;

IF(FALLING_EDGE(CLK))THEN --Èç¹ûʱÖÓÓÐϽµÑسöÏÖ£¬Ôò Q<=MEM(CONV_INTEGER(A));--¶Á³ö´æ´¢Æ÷ÖеÄÊý¾Ý END IF; END PROCESS; END BHV;

--½â2£ºÒÔͼ7-18´úÂëÐÎʽÉè¼ÆRAM

7-3 ÐÞ¸ÄÀý7-6£¬ÓÃGENERICÓï¾ä¶¨ÒåÀý7-6ÖеÄÊý¾ÝÏß¿íºÍ´æ´¢µ¥ÔªµÄÉî¶ÈµÄ²ÎÊý£¬ÔÙÉè¼ÆÒ»¸ö¶¥²ãÎļþÀý»¯Àý7-6¡£´Ë¶¥²ãÎļþÄܽ«²ÎÊý´«Èëµ×²ãÄ£¿éÀý7-6¡£¶¥²ãÎļþµÄ²ÎÊýÉèÊý¾Ý¿í¶È=16£¬´æ´¢Éî¶Èmsize=1024¡£

--½â1£ºÓÃGENERIC¶¨ÒåDBºÍABÐ޸ġ¾Àý7-6¡¿Éè¼ÆË«±ßÑØ¿ØÖƶÁдRAMµÄVHDL³ÌÐò¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;--´Ë³ÌÐò°üÀ¨º¬×ª»»º¯ÊýCONV_INTEGERlA) USE IEEE.STD_LOGIC_UNSIGNED.ALL;--´Ë³ÌÐò°ü°üº¬Ëã·ûÖØÔغ¯Êý ENTITY RAM7x8 IS

GENERIC(D_Bus: integer:=8;A_Bus: integer:=7;MEM_Num: integer:=128;init_file: string:=\

PORT( CLK: IN STD_LOGIC;--¶¨ÒåʱÖÓ WREN: IN STD_LOGIC;--¶¨ÒåдÔÊÐí¿ØÖÆ

A: IN STD_LOGIC_VECTOR(A_Bus-1 DOWNTO 0);--¶¨ÒåRAMµÄ7λµØÖ·ÊäÈë¶Ë¿Ú DIN: IN STD_LOGIC_VECTOR(D_Bus-1 DOWNTO 0);--¶¨ÒåRAMµÄ8λÊý¾ÝÊäÈë¶Ë¿Ú Q:OUT STD_LOGIC_VECTOR(D_Bus-1 DOWNTO 0));--¶¨ÒåRAMµÄ8λÊý¾ÝÊä³ö¶Ë¿Ú END;

ARCHITECTURE bhv OF RAM7x8 IS

TYPE G_ARRAY IS ARRAY(0 TO MEM_Num-1) OF STD_LOGIC_VECTOR(D_Bus-1 DOWNTO 0); SIGNAL MEM: G_ARRAY;--¶¨ÒåÐźÅMEMµÄÊý¾ÝÀàÐÍΪÓû§Ð¶¨ÒåµÄÀàÐÍG_ARRAY

attribute ram_init_file: string; --¶¨Òå×Ö·û´®ÊôÐԵıêʶ·ûram_init_file¡£ attribute ram_init_file of MEM: SIGNAL IS init_file; --¶¨Òå±êʶ·ûram_init_fileÊÇMEMµÄÊôÐÔ£¬

--²¢½«×Ö·û´®\³õʼ»¯¸³¸øram_init_file¡£

BEGIN

PROCESS(CLK)

BEGIN

IF RISING_EDGE(CLK) THEN

IF WREN='1' THEN --Èç¹ûʱÖÓÓÐÉÏÉýÑسöÏÖ£¬ÇÒдʹÄÜΪ¸ßµçƽ£¬Ôò MEM(CONV_INTEGER(A))<=DIN;--RAMÊý¾Ý¿ÚµÄÊý¾Ý±»Ð´ÈëÖ¸¶¨µØÖ·µÄµ¥Ôª END IF; END IF;

IF(FALLING_EDGE(CLK))THEN --Èç¹ûʱÖÓÓÐϽµÑسöÏÖ£¬Ôò Q<=MEM(CONV_INTEGER(A));--¶Á³ö´æ´¢Æ÷ÖеÄÊý¾Ý END IF; END PROCESS

--½â2£ºÓÃÀý»¯µ÷ÓÃÐ޸ĺóÀý7-6Éú³É10λABºÍ8λDBµÄRAM LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_ARITH.ALL;--´Ë³ÌÐò°üÀ¨º¬×ª»»º¯ÊýCONV_INTEGERlA) USE IEEE.STD_LOGIC_UNSIGNED.ALL;--´Ë³ÌÐò°ü°üº¬Ëã·ûÖØÔغ¯Êý ENTITY RAM10x8 IS

PORT( CLK: IN STD_LOGIC;--¶¨ÒåʱÖÓ WREN: IN STD_LOGIC;--¶¨ÒåдÔÊÐí¿ØÖÆ

A: IN STD_LOGIC_VECTOR(9 DOWNTO 0);--¶¨ÒåRAMµÄ10λµØÖ·ÊäÈë¶Ë¿Ú DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);--¶¨ÒåRAMµÄ8λÊý¾ÝÊäÈë¶Ë¿Ú Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--¶¨ÒåRAMµÄ8λÊý¾ÝÊä³ö¶Ë¿Ú END;

ARCHITECTURE bhv OF RAM10x8 IS

COMPONENT RAM7x8 --RAM7x8Ä£¿éµÄµ÷ÓÃÉùÃ÷

GENERIC(D_Bus: integer;A_Bus: integer;MEM_Num: integer;init_file: string); PORT( CLK: IN STD_LOGIC;--¶¨ÒåʱÖÓ WREN: IN STD_LOGIC;--¶¨ÒåдÔÊÐí¿ØÖÆ

A: IN STD_LOGIC_VECTOR(A_Bus-1 DOWNTO 0);--¶¨ÒåRAMµÄ7λµØÖ·ÊäÈë¶Ë¿Ú DIN: IN STD_LOGIC_VECTOR(D_Bus-1 DOWNTO 0);--¶¨ÒåRAMµÄ8λÊý¾ÝÊäÈë¶Ë¿Ú Q:OUT STD_LOGIC_VECTOR(D_Bus-1 DOWNTO 0));--¶¨ÒåRAMµÄ8λÊý¾ÝÊä³ö¶Ë¿Ú END COMPONENT; BEGIN

u1: RAM7x8 GENERIC MAP(D_Bus=>8,A_Bus=>10,MEM_Num=>1024,init_file=>\ PORT MAP(CLK,WREN,A,DIN,Q); END BHV;

7-4 ½¨Á¢Ò»¸öÔ­Àíͼ¶¥²ãÉè¼Æ¹¤³Ì£¬µ÷ÓÃLPM_RAM£¬½á¹¹²ÎÊýÓëÏ°Ìâ7-3Ïàͬ£¬³õʼ»¯ÎļþÊÇhex¸ñʽµÄÕýÏÒ²¨Êý¾ÝÎļþ¡£¸ø³öÉè¼ÆµÄ·ÂÕ沨ÐΡ£

½â£º7-4 ¶¥²ãÉè¼ÆÓÃÔ­Àíͼµ÷ÓÃLPM_RAM(½á¹¹²ÎÊýÓëÏ°Ìâ7-3Ïàͬ)

7-5(ÂÔ)²Î¿¼Quartus IIµÄHelp(Contents)£¬Ïêϸ˵Ã÷LPMÔª¼þaltcam¡¢altsyncram¡¢ LPM_fifo¡¢LPM_shiftregµÄʹÓ÷½·¨£¬ÒÔ¼°ÆäÖи÷²ÎÁ¿µÄº¬ÒåºÍÉèÖ÷½·¨¡£

8 Ï° Ìâ

8-1£¨5-1£©Ê²Ã´ÊǹÌÓÐÑÓʱ£¿Ê²Ã´ÊǹßÐÔÑÓʱ£¿P225~226 ´ð£º¹ÌÓÐÑÓʱ(Inertial Delay)Ò²³ÆΪ¹ßÐÔÑÓʱ£¬¹ÌÓÐÑÓʱµÄÖ÷ÒªÎïÀí»úÖÆÊÇ·Ö²¼µçÈÝЧӦ¡£

8-2£¨5-4£©ËµÃ÷ÐźźͱäÁ¿µÄ¹¦ÄÜÌص㣬ÒÔ¼°Ó¦ÓÃÉϵÄÒìͬµã¡£P208~P210

´ð£º±äÁ¿£º±äÁ¿ÊÇÒ»¸ö¾Ö²¿Á¿£¬Ö»ÄÜÔÚ½ø³ÌºÍ×Ó³ÌÐòÖÐʹÓᣱäÁ¿²»Äܽ«ÐÅÏ¢´ø³ö¶ÔËü×ö³ö¶¨ÒåµÄµ±Ç°½á¹¹¡£±äÁ¿µÄ¸³ÖµÊÇÒ»ÖÖÀíÏ뻯µÄÊý¾Ý´«Ê䣬ÊÇÁ¢¼´·¢ÉúµÄ£¬²»´æÔÚÈκÎÑÓʱÐÐΪ¡£±äÁ¿µÄÖ÷Òª×÷ÓÃÊÇÔÚ½ø³ÌÖÐ×÷ΪÁÙʱµÄÊý¾Ý´æ´¢µ¥Ôª¡£

ÐźţºÐźÅÊÇÃèÊöÓ²¼þϵͳµÄ»ù±¾Êý¾Ý¶ÔÏó£¬ÆäÐÔÖÊÀàËÆÓÚÁ¬½ÓÏߣ»¿É×÷ΪÉè¼ÆʵÌåÖв¢ÐÐÓï¾äÄ£¿é¼äµÄÐÅÏ¢½»Á÷ͨµÀ¡£ÐźŲ»µ«¿ÉÒÔÈÝÄɵ±Ç°Öµ£¬Ò²¿ÉÒÔ±£³ÖÀúÊ·Öµ£»Óë´¥·¢Æ÷µÄ¼ÇÒ书ÄÜÓкܺõĶÔÓ¦¹Øϵ¡£

8-3 ´Ó²»ÍêÕûµÄÌõ¼þÓï¾ä²úÉúʱÐòÄ£¿éµÄÔ­Àí¿´£¬Àý8-7ºÍ´Ó±íÃæÉÏ¿´¶¼°üº¬²»ÍêÕûÌõ¼þÓï¾ä£¬ÊÔ˵Ã÷£¬ÎªÊ²Ã´ËüÃǵÄ×ۺϽá¹û¶¼ÊÇ×éºÏµç·¡£ P214~P216 ´ð£º¸ù¾Ý±äÁ¿¾ßÓÐ˳ÐòÁ¢¼´¸³Öµ´«ËÍÌØÐÔ£¬Àý8-7ÖеIJ»ÍêÕûÌõ¼þÓï¾ä¶Ô±äÁ¿¸³ÖµÇ°¶Ô±äÁ¿½øÐгõʼֵÉèÖã»Ã¿´ÎÃô¸ÐÐźŴ¥·¢£¬¶Ô±äÁ¿µÄ¸³Öµ£¬×ÜÄܲúÉú½á¹û£¬ÎÞ±£³Ö״̬¡ª¡ª¼´Êä³öÊÇÊäÈëµÄº¯Êý£»Òò´Ë£¬Ö»ÄܲúÉú×éºÏÂß¼­µç·£»²»¿ÉÄܲúÉúʱÐòÂß¼­µç·¡£ --¡¾Àý8-7¡¿Ô¤Éè¼Æ4Ñ¡1¶à·Æ÷(ͨ¹ý±äÁ¿²âÑ¡ÔñÌõ¼þ£¬½«²úÉúÕýÈ·½á¹û¡£) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux4 IS

PORT(i0,i1,i2,i3,a,b: IN STD_LOGIC; q: OUT STD_LOGIC); END mux4;

ARCHITECTURE body_mux4 OF mux4 IS BEGIN

process(i0,i1,i2,i3,a,b)

variable muxval: integer range 7 DOWNTO 0; begin

muxval:=0;

if (a= '1') then muxval := muxval+1; end if; if (b= '1') then muxval := muxval+2; end if; case muxval is when 0=> q<=i0; when 1=> q<=i1; when 2=> q<=i2; when 3=> q<=i3;

when others=>q<='X'; --null; end case; end process; END body_mux4;

8-4 Éè¼ÆÒ»¸öÇó²¹ÂëµÄ³ÌÐò£¬ÊäÈëÊý¾ÝÊÇÒ»¸öÓзûºÅµÄ8λ¶þ½øÖÆÊý¡£

--½â£º8-4 Éè¼ÆÒ»¸öÇó²¹ÂëµÄ³ÌÐò£¬ÊäÈëÊý¾ÝÊÇÒ»¸öÓзûºÅµÄ8λ¶þ½øÖÆÊý¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY org_patch IS

PORT( org_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--Ô­ÂëÊäÈë patch_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--²¹ÂëÊä³ö END org_patch;

ARCHITECTURE BHV OF org_patch IS BEGIN

PROCESS(org_data) BEGIN

IF(org_data(7)='0') THEN

patch_data<=org_data; --org_data>=0£¬²¹Âë=Ô­Âë¡£ else

patch_data<=org_data(7)&(not org_data(6 DOWNTO 0))+1;--org_data<0£¬²¹Âë=|Ô­Âë|È¡·´+1¡£ END IF; END PROCESS; END BHV;

8-5 Éè¼ÆÒ»¸ö±È½Ïµç·£¬µ±ÊäÈëµÄ8421BCDÂë´óÓÚ5ʱÊä³ö1£¬·ñÔòÊä³ö0¡£ --½â£º8-5 Éè¼ÆÒ»¸ö±È½Ïµç·£¬µ±ÊäÈëµÄ8421BCDÂë´óÓÚ5ʱÊä³ö1£¬·ñÔòÊä³ö0¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY g_5_cmp IS

PORT( d_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --ÊäÈëÊý¾Ý

cmp_out : OUT STD_LOGIC); --±È½ÏÊä³ö(1:ÊäÈëÊý¾Ý>5) END g_5_cmp;

ARCHITECTURE BHV OF g_5_cmp IS BEGIN

PROCESS(d_in) BEGIN

IF(d_in>\

cmp_out<='1'; --ÊäÈëÊý¾Ý´óÓÚ5£¬±È½ÏÊä³ö1¡£ else

cmp_out<='0'; --ÊäÈëÊý¾ÝСÓÚµÈÓÚ5£¬±È½ÏÊä³ö0¡£ END IF; END PROCESS; END BHV;

8-6 ÓÃÔ­Àíͼ»òVHDLÊäÈ뷽ʽ·Ö±ðÉè¼ÆÒ»¸öÖÜÆÚÐÔ²úÉú¶þ½øÖÆÐòÁÐ01001011001µÄÐòÁз¢ÉúÆ÷£¬ÓÃÒÆλ¼Ä´æÆ÷»òÓÃͬ²½Ê±Ðòµç·ʵÏÖ£¬²¢ÓÃʱÐò·ÂÕæÆ÷ÑéÖ¤Æ书ÄÜ¡£(¿ÉÔ¤ÖÃÊý11λÐòÁз¢ÉúÆ÷)

½â(1)£ºÓÃÔ­ÀíͼÉè¼Æ²úÉú01001011001ÐòÁÐ

½â(2)£ºÓÃVHDLÉè¼Æ²úÉú01001011001ÐòÁÐ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY S_generator IS

PORT(CLK,CLR: IN STD_LOGIC; --¹¤×÷ʱÖÓ/¸´Î»ÐźŠS_out: OUT STD_LOGIC);--ÐòÁÐÊä³öλ END S_generator;

ARCHITECTURE behav OF S_generator IS

SIGNAL D: STD_LOGIC_VECTOR(10 DOWNTO 0);--11λѭ»·ÒÆλ¼Ä´æÆ÷ BEGIN

PROCESS(CLK,CLR) BEGIN

IF CLK'EVENT AND CLK='1' THEN --ʱÖÓµ½À´Ê±£¬Öðλ×óÒÆÑ­»·Êä³öÐòÁÐλ IF CLR='1' THEN D<=\¸´Î»²Ù×÷£¬²úÉú11λ´ýÊä³öÐòÁÐ ELSE

D(10 DOWNTO 1)<=D(9 DOWNTO 0); D(0)<=D(10); S_out<=D(10); END IF; END IF; END PROCESS; END behav;

½â(3£º)ÓÃÔ­ÀíͼÉè¼ÆÇÒ¿ÉÔ¤ÖÃÊýµÄ11λÐòÁÐ

8-7 ½«Àý8-11(ÓûÉè¼Æ4Ñ¡1Èý̬×ÜÏß)ÖеÄËĸöIFÓï¾ä·Ö±ðÓÃËĸö²¢Áнø³ÌÓï¾ä±í´ï³öÀ´¡£

--8-7 Ð޸ġ¾Àý8-11¡¿(ÓûÉè¼Æ4Ñ¡1Èý̬×ÜÏß)£¬ÓÃ4¸ö½ø³ÌÉè¼Æ4Ñ¡1ͨµÀÈý̬×ÜÏß(8λ)µç· LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS

port(input3,input2,input1,input0 :

IN STD_LOGIC_VECTOR(7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY tristate2 ;

ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN

COM3: PROCESS(enable,input3) BEGIN

IF enable=\ END PROCESS;

COM2: PROCESS(enable,input2) BEGIN

IF enable=\ END PROCESS;

COM1: PROCESS(enable,input1) BEGIN

IF enable=\ END PROCESS;

COM0: PROCESS(enable,input0) BEGIN

IF enable=\ END PROCESS;

END ARCHITECTURE multiple_drivers;

10 Ï° Ìâ

10-1 ¾Ù¶þÀý˵Ã÷£¬ÓÐÄÄЩ³£ÓÃʱÐòµç·ÊÇ״̬»ú±È½ÏµäÐ͵ÄÌØÊâÐÎʽ£¬²¢ËµÃ÷ËüÃÇÊôÓÚʲôÀàÐ͵Ä״̬»ú(±àÂëÀàÐÍ¡¢Ê±ÐòÀàÐͺͽṹÀàÐÍ)¡££¨Ìáʾ£º¶þ½øÖƼÆÊýÆ÷¡¢¡°00000001¡±×óÑ­»·ÒÆλ¼Ä´æÆ÷£©

½â£º1£©¶þ½øÖƼÆÊýÆ÷¡¢Ñ­»·ÒÆλ¼Ä´æÆ÷¡£

2£©¶þ½øÖƼÆÊýÆ÷£ºMooreÐÍ״̬»ú£»Ë³Ðò±àÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ 3£©¡°00000001¡±×óÑ­»·ÒÆλ¼Ä´æÆ÷£ºMooreÐÍ״̬»ú£»Ò»Î»ÈÈÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£

--(1)¼ÆÊýÆ÷£ºMooreÐÍ״̬»ú£»Ë³Ðò±àÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT IS

PORT(CLK: IN STD_LOGIC;

Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC); END COUNT;

ARCHITECTURE behav OF COUNT IS

type STATE is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15); type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(3 DOWNTO 0);

constant val_arr_STATE: arr_STATE:=(\ \

SIGNAL cs: STATE; BEGIN

PROCESS(cs)

BEGIN --ʱÐò×éºÏÖ÷¿Ø½ø³Ì£¬´Î̬ת»» IF CLK'EVENT AND CLK='1' THEN CASE cs IS

WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s8; WHEN s8 => cs<=s9; WHEN s9 => cs<=s10; WHEN s10=> cs<=s11; WHEN s11=> cs<=s12; WHEN s12=> cs<=s13; WHEN s13=> cs<=s14; WHEN s14=> cs<=s15; WHEN s15=> cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF;

IF cs=s15 then COUT<='1'; else COUT<='0'; END IF; END PROCESS;

Q<=val_arr_STATE(cs); END behav;

--(2)\×óÑ­»·ÒÆλ¼Ä´æÆ÷£ºMooreÐÍ״̬»ú£»Ò»Î»ÈÈÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LEFT_SHIFT IS

PORT(CLK: IN STD_LOGIC;

Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Cy: OUT STD_LOGIC); END LEFT_SHIFT;

ARCHITECTURE behav OF LEFT_SHIFT IS

type STATE is(s0,s1,s2,s3,s4,s5,s6,s7);

type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(7 DOWNTO 0);

constant val_arr_STATE: arr_STATE:=(\ \

SIGNAL cs: STATE; BEGIN

PROCESS(cs)

BEGIN --ʱÐò×éºÏÖ÷¿Ø½ø³Ì£¬´Î̬ת»» IF CLK'EVENT AND CLK='1' THEN CASE cs IS

WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF; END PROCESS;

Q<=val_arr_STATE(cs); Cy<=val_arr_STATE(cs)(7); END behav;

10-2 ÐÞ¸ÄÀý10-1£¬½«ÆäÖ÷¿Ø×éºÏ½ø³Ì·Ö½âΪÁ½¸ö½ø³Ì£¬Ò»¸ö¸ºÔð״̬ת»»£¬ÁíÒ»¸ö¸ºÔðÊä³ö¿ØÖÆÐźš£

--10-2 ÐÞ¸ÄÀý10-1£¬½«ÆäÖ÷¿Ø×éºÏ½ø³Ì·Ö½âΪÁ½¸ö½ø³Ì£¬Ò»¸ö¸ºÔð״̬ת»»£¬ÁíÒ»¸ö¸ºÔðÊä³ö¿ØÖÆÐźš£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS

PORT(clk,reset : IN STD_LOGIC;--Ö÷¿ØʱÐò½ø³ÌʱÖÓÇý¶¯ºÍ¸´Î»ÐźÅ

state_inputs : IN STD_LOGIC_VECTOR (0 TO 1);--ÍⲿÊäÈëÐźŠcomb_outputs :OUT INTEGER RANGE 0 TO 15 ); --¶ÔÍâÊä³öÐźŠEND s_machine;

ARCHITECTURE behv OF s_machine IS

TYPE FSM_ST IS (s0, s1, s2, s3); --Êý¾ÝÀàÐͶ¨Ò壬״̬·ûºÅ»¯ SIGNAL c_st, next_state: FSM_ST;--½«ÏÖ̬ºÍ´Î̬¶¨ÒåΪеÄÊý¾ÝÀàÐÍ BEGIN

REG: PROCESS (reset,clk) BEGIN

IF reset ='0' THEN c_st <= s0;--¼ì²âÒì²½¸´Î»ÐźŠELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF; END PROCESS;

COM1: PROCESS(c_st, state_Inputs)--Ö÷¿Ø×éºÏ½ø³Ì(ÏÖ̬ºÍÍⲿÊäÈëΪÃô¸ÐÐźÅ) BEGIN

CASE c_st IS

WHEN s0 => IF state_inputs = \ÊäÈëΪ¡°00¡±£¬ÔÚs0̤²½ ELSE next_state<=s1;END IF;--·ñÔò½øÈës1 WHEN s1 => IF state_inputs = \ÊäÈëΪ¡°00¡±£¬ÔÚs1̤²½ ELSE next_state<=s2;END IF; --·ñÔò½øÈës2 WHEN s2 => IF state_inputs = \ÊäÈëΪ¡°11¡±£¬½øÈës0 ELSE next_state<=s3;END IF; --·ñÔò½øÈës3 WHEN s3 => IF state_inputs = \ÊäÈëΪ¡°11¡±£¬ÔÚs3̤²½ ELSE next_state<=s0;END IF; --·ñÔò·µ»Øs0 END case; END PROCESS;

COM2: PROCESS(c_st, state_Inputs)--Ö÷¿Ø×éºÏ½ø³Ì(ÏÖ̬ºÍÍⲿÊäÈëΪÃô¸ÐÐźÅ) BEGIN

CASE c_st IS

WHEN s0 => comb_outputs<= 5; --ÏÖ̬Ϊs0ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ5±àÂë WHEN s1 => comb_outputs<= 8; --ÏÖ̬Ϊs1ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ8±àÂë WHEN s2 => comb_outputs<= 12; --ÏÖ̬Ϊs2ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ12±àÂë WHEN s3 => comb_outputs<= 14; --ÏÖ̬Ϊs3ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ14±àÂë END case; END PROCESS; END behv;

10-3 ¸ÄдÀý10-1£¬Óú궨ÒåÓï¾ä¶¨Òå״̬±äÁ¿£¬¸ø³ö·ÂÕ沨ÐÎ(º¬×´Ì¬±äÁ¿)£¬Óëͼ10-3×÷±È½Ï¡£×¢ÒâÉèÖÃÊʵ±µÄ״̬»úÔ¼ÊøÌõ¼þ¡£

--10-3 ¸ÄдÀý10-1£¬Óú궨ÒåÓï¾ä¶¨Òå״̬±äÁ¿£¬¸ø³ö·ÂÕ沨ÐÎ(º¬×´Ì¬±äÁ¿)£¬Óëͼ10-3×÷±È½Ï¡£×¢ÒâÉèÖÃÊʵ±µÄ״̬»úÔ¼ÊøÌõ¼þ¡£ LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS

PORT(clk,reset : IN STD_LOGIC;--Ö÷¿ØʱÐò½ø³ÌʱÖÓÇý¶¯ºÍ¸´Î»ÐźŠstate_inputs : IN STD_LOGIC_VECTOR (0 TO 1);--ÍⲿÊäÈëÐźŠcomb_outputs :OUT INTEGER RANGE 0 TO 15 ); --¶ÔÍâÊä³öÐźŠEND s_machine;

ARCHITECTURE behv OF s_machine IS

-- TYPE FSM_ST IS (s0, s1, s2, s3); --Êý¾ÝÀàÐͶ¨Ò壬״̬·ûºÅ»¯ -- attribute syn_encoding

: string;

-- attribute syn_encoding of FSM_ST : type is \

SIGNAL c_st, next_state: STD_LOGIC_VECTOR(1 DOWNTO 0);--FSM_ST;--½«ÏÖ̬ºÍ´Î̬¶¨ÒåΪеÄÊý¾ÝÀàÐÍ

CONSTANT s0: STD_LOGIC_VECTOR(1 DOWNTO 0):=\״̬·ûºÅ±àÂ붨Òå CONSTANT s1: STD_LOGIC_VECTOR(1 DOWNTO 0):=\ CONSTANT s2: STD_LOGIC_VECTOR(1 DOWNTO 0):=\ CONSTANT s3: STD_LOGIC_VECTOR(1 DOWNTO 0):=\BEGIN

REG: PROCESS (reset,clk) BEGIN

IF reset ='0' THEN c_st <= s0;--¼ì²âÒì²½¸´Î»ÐźŠELSIF clk='1' AND clk'EVENT THEN c_st <= next_state; END IF; END PROCESS;

COM:PROCESS(c_st, state_Inputs)--Ö÷¿Ø×éºÏ½ø³Ì(ÏÖ̬ºÍÍⲿÊäÈëΪÃô¸ÐÐźÅ) BEGIN

CASE c_st IS

WHEN s0 => comb_outputs<= 5; --ÏÖ̬Ϊs0ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ5±àÂë IF state_inputs = \ÊäÈëΪ¡°00¡±£¬ÔÚs0̤²½ ELSE next_state<=s1;END IF; --·ñÔò½øÈës1 WHEN s1 => comb_outputs<= 8; --ÏÖ̬Ϊs1ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ8±àÂë IF state_inputs = \ÊäÈëΪ¡°00¡±£¬ÔÚs1̤²½ ELSE next_state<=s2;END IF; --·ñÔò½øÈës2 WHEN s2 => comb_outputs<= 12; --ÏÖ̬Ϊs2ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ12±àÂë IF state_inputs = \ÊäÈëΪ¡°11¡±£¬½øÈës0 ELSE next_state<=s3;END IF; --·ñÔò½øÈës3 WHEN s3 => comb_outputs<= 14; --ÏÖ̬Ϊs3ʱ£¬¶ÔÍâÊä³öÃüÁîÐźÅ14±àÂë IF state_inputs = \ÊäÈëΪ¡°11¡±£¬ÔÚs3̤²½ ELSE next_state<=s0;END IF; --·ñÔò·µ»Øs0 END case; END PROCESS; END behv;

10-4 ΪÀý10-2µÄLOCKÐźÅÔö¼ÓkeepÊôÐÔ£¬ÔÙ¸ø³ö´ËÉè¼ÆµÄ·ÂÕ沨ÐÎ(×¢ÒâɾȥLOCK_T)¡£

--10-4 ΪÀý10-2(MooreÐÍADC0809²ÉÑù)µÄLOCKÐźÅÔö¼ÓkeepÊôÐÔ¡£

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