begin
LD_6_RADIO <= 0;
end
end always@(posedge CP_1Hz) if(Minute[7:0]==8'h00) begin
counter[7:0]<=counter[7:0]+1'b1; end else begin
counter[7:0]<=8'h00;
end
endmodule
五、 顶层模块设计图
六、 子模块设计
1、50MHz分频器
module Divider50MHz(CLK_50M,nCLR,CLK_1HzOut);
parameter N = 25;
//位宽
parameter CLK_Freq = 50000000; //50MHz时钟输入 parameter OUT_Freq = 1; input nCLR,CLK_50M;
//1Hz时钟输出
//输入端口说明
output reg CLK_1HzOut; reg [N-1:0] Count_DIV;
//输出端口说明
//内部节点，存放计数器的输出值
always@(posedge CLK_50M or negedge nCLR) begin
if(!nCLR) begin CLK_1HzOut <= 0; Count_DIV <= 0; end else begin
if(Count_DIV <(CLK_Freq/(2*OUT_Freq)-1))//计数器模 Count_DIV <= Count_DIV + 1'b1; else begin Count_DIV <= 0;
//分频器输出清零
//输出信号取反 //分频器计数加1
CLK_1HzOut <= ~CLK_1HzOut; end end
end
endmodule
2、秒模10计数器
module Scounter10(Q,nCR,EN,CP);
input CP,nCR,EN; output Q; reg [3:0] Q;
always @(posedge CP or negedge nCR)
begin
if(~nCR) Q <= 4'b0000;//异步清零 else if(~EN) Q <= Q; //暂停计数 else if(Q==4'b1001) Q <= 4'b0000; else Q <= Q + 1'b1;
end
3、秒模6计数器
module Scounter6(Q,nCR,EN,CP);
input CP,nCR,EN; output Q; reg [3:0] Q;
always @(posedge CP or negedge nCR) begin
if(~nCR) Q <= 4'b0000;//异步清零 else if(~EN) Q <= Q; //暂停计数 else if(Q==4'b0101) Q <= 4'b0000; else Q <= Q + 1'b1;
end
4、分模10计数器
module Mcounter10(Q,nCR,EN1,EN2,CP);