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unit<=unitcount; end process; end;
3分计数模块： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity min is
port(rst,carry,en : in std_logic; ADJclk,ADJEN : in std_logic;
ADJ : in std_logic_vector(3 downto 0); carryout : out std_logic;
decade,unit : out std_logic_vector(3 downto 0)); end ;
architecture bhv of min is
signal clk : std_logic; begin
process(carry,ADJ,ADJEN,ADJclk) begin
if (ADJEN='1' and ADJ=\ else clk<=carry; end if; end process;
process(rst,en,clk,ADJEN)
variable unitcount : std_logic_vector(3 downto 0); variable decadecount : std_logic_vector(3 downto 0); begin
if (rst='1') then unitcount:=\ elsif(en='1') then
if (clk 'event and clk='1')then
if(unitcount<10) then unitcount:=unitcount+1; else unitcount:=\ end if;
if(unitcount=10) then decadecount:=decadecount+1; unitcount:=\
end if;
if(decadecount=6 and unitcount=0) then unitcount:=\
if ADJEN='0' then carryout<='1'; -- when ADJEN=1,donot generate carry
else carryout<='0';
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end if;
else carryout<='0'; end if; end if; end if;
decade<=decadecount; unit<=unitcount; end process; end;
4秒计数模块： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sec is
port(rst,clk,en : in std_logic; ADJEN : in std_logic; carryout : out std_logic;
decade,unit : out std_logic_vector(3 downto 0)); end ;
architecture bhv of sec is begin
process(rst,en,clk)
variable unitcount : std_logic_vector(3 downto 0); variable decadecount : std_logic_vector(3 downto 0); begin
if (rst='1') then unitcount:=\ elsif(en='1') then
if clk'event and clk='1'then
if(unitcount<10) then unitcount:=unitcount+1; else unitcount:=\ end if;
if(unitcount=10) then decadecount:=decadecount+1; unitcount:=\ end if;
if(decadecount=6 and unitcount=0)
then unitcount:=\
if(ADJEN='0') then carryout<='1'; -- when ADJEN=1, donot generate carry
else carryout<='0'; end if;
else carryout<='0'; end if; end if;
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end if;
decade<=decadecount; unit<=unitcount; end process; end;
5闹钟模块： library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity alarm is
port(clk,en,ADJclk : in std_logic; alarmADJ : in std_logic; AlarmEn : in std_logic;
ADJ : in std_logic_vector(3 downto 0); hour_unit : in std_logic_vector(3 downto 0); hour_decade : in std_logic_vector(3 downto 0); min_unit : in std_logic_vector(3 downto 0); min_decade : in std_logic_vector(3 downto 0); ADJhour_unit : out std_logic_vector(3 downto 0); ADJhour_decade : out std_logic_vector(3 downto 0); ADJmin_unit : out std_logic_vector(3 downto 0); ADJmin_decade : out std_logic_vector(3 downto 0); sound : out std_logic); end;
architecture bhv of alarm is
signal hour1,hour2,min1,min2 : std_logic_vector(3 downto 0); begin
process(en,alarmADJ,ADJ,ADJclk) variable
hour_decadecounnt,hour_unitcount,min_decadecount,min_unitcount std_logic_vector(3 downto 0); begin
if (en='1' and alarmADJ='1') then
if ADJclk 'event and ADJclk='1' then if ADJ=\
if(hour_unitcount<10) hour_unitcount:=hour_unitcount+1;
else hour_unitcount:=\ end if;
if(hour_unitcount=10) hour_decadecounnt:=hour_decadecounnt+1;hour_unitcount:=\ end if;
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if(hour_decadecounnt=2 and hour_unitcount=4) then hour_decadecounnt:=\ end if;
elsif ADJ=\ if(min_unitcount<10) then min_unitcount:=min_unitcount+1;
else min_unitcount:=\ end if;
if(min_unitcount=10) then min_decadecount:=min_decadecount+1;min_unitcount:=\ end if;
if(min_decadecount=6 and min_unitcount=0) then min_decadecount:=\ end if; end if; end if; end if;
hour1<=hour_decadecounnt; hour2<=hour_unitcount; min1<=min_decadecount; min2<=min_unitcount; end process;
process(en,AlarmEn,ADJclk,clk,hour_unit,hour_decade,min_unit,min_decade,hour1,hour2,min1,min2)
variable count : std_logic_vector(3 downto 0); begin
if(en='1' and AlarmEn='1') then
if(hour_unit=hour2 and hour_decade=hour1 and min_unit=min2 and min_decade=min1) then
if clk 'event and clk='1' then
if (count<10) then count:=count+1; else sound<='0'; end if; end if;
if(count<10) then sound<= ADJclk; end if;
else count:=\ end if; end if;
ADJhour_decade<=hour1; ADJhour_unit<=hour2; ADJmin_decade<=min1; ADJmin_unit<=min2;
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