19.1 TIM¼Ä´æÆ÷½á¹¹ ....................................................................242 19.2 TIM¿âº¯Êý ........................................................................244 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 º¯ÊýÃû TIM_DeInit TIM_TimeBaseInit TIM_OCInit TIM_ICInit TIM_TimeBaseStructInit TIM_OCStructInit TIM_ICStructInit TIM_Cmd TIM _ITConfig TIM_DMAConfig TIM_DMACmd TIM_InternalClockConfig TIM_ITRxExternalClockConfig TIM_TIxExternalClockConfig TIM_ETRClockMode1Config TIM_ETRClockMode2Config TIM_ETRConfig TIM_SelectInputTrigger TIM_PrescalerConfig TIM_CounterModeConfig TIM_ForcedOC1Config TIM_ForcedOC2Config TIM_ForcedOC3Config TIM_ForcedOC4Config TIM_ARRPreloadConfig TIM_SelectCCDMA TIM_OC1PreloadConfig TIM_OC2PreloadConfig TIM_OC3PreloadConfig TIM_OC4PreloadConfig TIM_OC1FastConfig TIM_OC2FastConfig TIM_OC3FastConfig TIM_OC4FastConfig TIM_ClearOC1Ref TIM_ClearOC2Ref TIM_ClearOC3Ref TIM_ClearOC4Ref TIM_UpdateDisableConfig TIM_EncoderInterfaceConfig TIM_GenerateEvent TIM_OC1PolarityConfig TIM_OC2PolarityConfig TIM_OC3PolarityConfig TIM_OC4PolarityConfig TIM_UpdateRequestConfig TIM_SelectHallSensor TIM_SelectOnePulseMode TIM_SelectOutputTrigger TIM_SelectSlaveMode ÃèÊö ½«ÍâÉèTIMx¼Ä´æÆ÷ÖØÉèΪȱʡֵ ¸ù¾ÝTIM_TimeBaseInitStructÖÐÖ¸¶¨µÄ²ÎÊý³õʼ»¯TIMxµÄʱ¼ä»ùÊýµ¥Î» ¸ù¾ÝTIM_OCInitStructÖÐÖ¸¶¨µÄ²ÎÊý³õʼ»¯ÍâÉèTIMx ¸ù¾ÝTIM_ICInitStructÖÐÖ¸¶¨µÄ²ÎÊý³õʼ»¯ÍâÉèTIMx °ÑTIM_TimeBaseInitStructÖеÄÿһ¸ö²ÎÊý°´È±Ê¡ÖµÌîÈë °ÑTIM_OCInitStructÖеÄÿһ¸ö²ÎÊý°´È±Ê¡ÖµÌîÈë °ÑTIM_ICInitStructÖеÄÿһ¸ö²ÎÊý°´È±Ê¡ÖµÌîÈë ʹÄÜ»òÕßʧÄÜTIMxÍâÉè ʹÄÜ»òÕßʧÄÜÖ¸¶¨µÄTIMÖÐ¶Ï ÉèÖÃTIMxµÄDMA½Ó¿Ú ʹÄÜ»òÕßʧÄÜÖ¸¶¨µÄTIMxµÄDMAÇëÇó ÉèÖÃTIMxÄÚ²¿Ê±ÖÓ ÉèÖÃTIMxÄÚ²¿´¥·¢ÎªÍⲿʱÖÓģʽ ÉèÖÃTIMx´¥·¢ÎªÍⲿʱÖÓ ÅäÖÃTIMxÍⲿʱÖÓģʽ1 ÅäÖÃTIMxÍⲿʱÖÓģʽ2 ÅäÖÃTIMxÍⲿ´¥·¢ Ñ¡ÔñTIMxÊäÈë´¥·¢Ô´ ÉèÖÃTIMxÔ¤·ÖƵ ÉèÖÃTIMx¼ÆÊýÆ÷ģʽ ÖÃTIMxÊä³ö1Ϊ»î¶¯ »ò ·Ç»î¶¯µçƽ ÖÃTIMxÊä³ö2Ϊ»î¶¯ »ò ·Ç»î¶¯µçƽ ÖÃTIMxÊä³ö3Ϊ»î¶¯ »ò ·Ç»î¶¯µçƽ ÖÃTIMxÊä³ö4Ϊ»î¶¯ »ò ·Ç»î¶¯µçƽ ʹÄÜ»òÕßʧÄÜTIMxÔÚARRÉϵÄԤװÔؼĴæÆ÷ Ñ¡ÔñTIMxÍâÉèµÄ²¶»ñ±È½ÏDMAÔ´ ʹÄÜ»òʧÄÜTIMxÔÚCCR1ÉϵÄԤװÔؼĴæÆ÷ ʹÄÜ»òʧÄÜTIMxÔÚCCR2ÉϵÄԤװÔؼĴæÆ÷ ʹÄÜ»òʧÄÜTIMxÔÚCCR3ÉϵÄԤװÔؼĴæÆ÷ ʹÄÜ»òʧÄÜTIMxÔÚCCR4ÉϵÄԤװÔؼĴæÆ÷ ÉèÖÃTIMx²¶»ñ±È½Ï1¿ìËÙÌØÕ÷ ÉèÖÃTIMx²¶»ñ±È½Ï2¿ìËÙÌØÕ÷ ÉèÖÃTIMx²¶»ñ±È½Ï3¿ìËÙÌØÕ÷ ÉèÖÃTIMx²¶»ñ±È½Ï4¿ìËÙÌØÕ÷ ÔÚÒ»¸öÍⲿʼþʱÇå³ý»ò±£³ÖOCREF1ÐźŠÔÚÒ»¸öÍⲿʼþʱÇå³ý»ò±£³ÖOCREF2ÐźŠÔÚÒ»¸öÍⲿʼþʱÇå³ý»ò±£³ÖOCREF3ÐźŠÔÚÒ»¸öÍⲿʼþʱÇå³ý»ò±£³ÖOCREF4ÐźŠʹÄÜ»òÕßʧÄÜTIMx¸üÐÂʼþ ÉèÖÃTIMx±àÂë½çÃæ ÉèÖÃTIMxʼþÓÉÈí¼þ²úÉú ÉèÖÃTIMxͨµÀ1¼«ÐÔ ÉèÖÃTIMxͨµÀ2¼«ÐÔ ÉèÖÃTIMxͨµÀ3¼«ÐÔ ÉèÖÃTIMxͨµÀ4¼«ÐÔ ÉèÖÃTIMx¸üÐÂÇëÇóÔ´ ʹÄÜ»òÕßʧÄÜTIMx»ô¶û´«¸ÐÆ÷½Ó¿Ú ÉèÖÃTIMxµ¥Âö³åģʽ Ñ¡ÔñTIMx´¥·¢Êä³öģʽ Ñ¡ÔñTIMx´Óģʽ 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TIM_SelectMasterSlaveMode TIM_SetCounter TIM_SetAutoreload TIM_SetCompare1 TIM_SetCompare2 TIM_SetCompare3 TIM_SetCompare4 TIM_SetIC1Prescaler TIM_SetIC2Prescaler TIM_SetIC3Prescaler TIM_SetIC4Prescaler TIM_SetClockDivision TIM_GetCapture1 TIM_GetCapture2 TIM_GetCapture3 TIM_GetCapture4 TIM_GetCounter TIM_GetPrescaler TIM_GetFlagStatus TIM_ClearFlag TIM_GetITStatus TIM_ClearITPendingBit ÉèÖûòÕßÖØÖÃTIMxÖ÷/´Óģʽ ÉèÖÃTIMx¼ÆÊýÆ÷¼Ä´æÆ÷Öµ ÉèÖÃTIMx×Ô¶¯ÖØ×°ÔؼĴæÆ÷Öµ ÉèÖÃTIMx²¶»ñ±È½Ï1¼Ä´æÆ÷Öµ ÉèÖÃTIMx²¶»ñ±È½Ï2¼Ä´æÆ÷Öµ ÉèÖÃTIMx²¶»ñ±È½Ï3¼Ä´æÆ÷Öµ ÉèÖÃTIMx²¶»ñ±È½Ï4¼Ä´æÆ÷Öµ ÉèÖÃTIMxÊäÈ벶»ñ1Ô¤·ÖƵ ÉèÖÃTIMxÊäÈ벶»ñ2Ô¤·ÖƵ ÉèÖÃTIMxÊäÈ벶»ñ3Ô¤·ÖƵ ÉèÖÃTIMxÊäÈ벶»ñ4Ô¤·ÖƵ ÉèÖÃTIMxµÄʱÖÓ·Ö¸îÖµ »ñµÃTIMxÊäÈ벶»ñ1µÄÖµ »ñµÃTIMxÊäÈ벶»ñ2µÄÖµ »ñµÃTIMxÊäÈ벶»ñ3µÄÖµ »ñµÃTIMxÊäÈ벶»ñ4µÄÖµ »ñµÃTIMx¼ÆÊýÆ÷µÄÖµ »ñµÃTIMxÔ¤·ÖƵֵ ¼ì²éÖ¸¶¨µÄTIM±ê־λÉèÖÃÓë·ñ Çå³ýTIMxµÄ´ý´¦Àí±ê־λ ¼ì²éÖ¸¶¨µÄTIMÖжϷ¢ÉúÓë·ñ Çå³ýTIMxµÄÖжϴý´¦Àíλ 19 ͨÓö¨Ê±Æ÷£¨TIM£©
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Section 19.1 TIM¼Ä´æÆ÷½á¹¹ÃèÊöÁ˹̼þº¯Êý¿âËùʹÓõÄÊý¾Ý½á¹¹£¬Section 19.2 ¹Ì¼þ¿âº¯Êý½éÉÜÁ˺¯Êý¿âÀïµÄËùÓк¯Êý¡£
19.1 TIM¼Ä´æÆ÷½á¹¹
TIM ¼Ä´æÆ÷½á¹¹£¬TIM_TypeDeff£¬ÔÚÎļþ¡°stm2f10x_map.h¡±Öж¨ÒåÈçÏ£º
typedef struct {
vu16 CR1;
u16 RESERVED0; vu16 CR2;
u16 RESERVED1; vu16 SMCR;
u16 RESERVED2; vu16 DIER;
u16 RESERVED3; vu16 SR;
u16 RESERVED4; vu16 EGR;
u16 RESERVED5; vu16 CCMR1; u16 RESERVED6; vu16 CCMR2; u16 RESERVED7; vu16 CCER;
u16 RESERVED8; vu16 CNT;
u16 RESERVED9; vu16 PSC;
u16 RESERVED10; vu16 ARR;
u16 RESERVED11[3]; vu16 CCR1;
u16 RESERVED12; vu16 CCR2;
u16 RESERVED13; vu16 CCR3;
u16 RESERVED14; vu16 CCR4;
u16 RESERVED15[3]; vu16 DCR;
u16 RESERVED16; vu16 DMAR;
u16 RESERVED17; }TIM_TypeDef;
Table 457.Àý¾ÙÁËTIMËùÓмĴæÆ÷ No ¼Ä´æÆ÷ ÃèÊö 1 CR1 ¿ØÖƼĴæÆ÷1 2 CR2 ¿ØÖƼĴæÆ÷2 3 SMCR ´Óģʽ¿ØÖƼĴæÆ÷ 4 DIER DMA/ÖжÏʹÄܼĴæÆ÷ 5 SR ״̬¼Ä´æÆ÷ 6 EGR ʼþ²úÉú¼Ä´æÆ÷ 7 CCMR1 ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷1 8 CCMR2 ²¶»ñ/±È½Ïģʽ¼Ä´æÆ÷2 9 CCER ²¶»ñ/±È½ÏʹÄܼĴæÆ÷ 10 CNT ¼ÆÊýÆ÷¼Ä´æÆ÷ 11 PSC Ô¤·ÖƵ¼Ä´æÆ÷ 12 APR ×Ô¶¯ÖØ×°ÔؼĴæÆ÷ 13 CCR1 ²¶»ñ/±È½Ï¼Ä´æÆ÷1 14 CCR2 ²¶»ñ/±È½Ï¼Ä´æÆ÷2 15 CCR3 ²¶»ñ/±È½Ï¼Ä´æÆ÷3 16 CCR4 ²¶»ñ/±È½Ï¼Ä´æÆ÷4 17 DCR DMA¿ØÖƼĴæÆ÷ 18 DMAR Á¬ÐøģʽµÄDMAµØÖ·¼Ä´æÆ÷ Èý¸ö TIM ÍâÉèÉùÃ÷ÓÚÎļþ£º ...
#define PERIPH_BASE ((u32)0x40000000) #define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) ...
#ifndef DEBUG ...
#ifdef _TIM2
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) #endif /*_TIM2 */ #ifdef _TIM3
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) #endif /*_TIM3 */ #ifdef _TIM4
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) #endif /*_TIM4 */ ...
#else /* DEBUG */ ...
#ifdef _TIM2
EXT TIM_TypeDef *TIM2; #endif /*_TIM2 */ #ifdef _TIM3
EXT TIM_TypeDef *TIM3; #endif /*_TIM3 */ #ifdef _TIM4
EXT TIM_TypeDef *TIM4; #endif /*_TIM4 */ ... #endif
ʹÓÃDebugģʽʱ£¬³õʼ»¯Ö¸ÕëTIM2, TIM3ºÍTIM4ÓÚÎļþ¡°st32f10x_lib.c¡±£º
...
#ifdef _TIM2
TIM2 = (TIM_TypeDef *) TIM2_BASE; #endif /*_TIM2 */ #ifdef _TIM3
TIM3 = (TIM_TypeDef *) TIM3_BASE; #endif /*_TIM3 */ #ifdef _TIM4
TIM4 = (TIM_TypeDef *) TIM4_BASE; #endif /*_TIM4 */ ...
ΪÁË·ÃÎÊ TIM ¼Ä´æÆ÷£¬, _TIM£¬_TIM2, _TIM3ºÍ_TIM4 ±ØÐëÔÚÎļþ¡°stm2f10x_conf.h¡±Öж¨ÒåÈçÏ£º
...
#define _TIM #define _TIM2 #define _TIM3 #define _TIM4 ...
19.2 TIM¿âº¯Êý
Table 458. TIM¿âº¯Êý ¡¾¼ûÊ×Ò³¡¿
19.2.1 º¯ÊýTIM_DeInit
Table 459.º¯ÊýTIM_DeInit º¯ÊýÃû TIM_DeInit º¯ÊýÔÐÎ void TIM_DeInit(TIM_TypeDef* TIMx) ¹¦ÄÜÃèÊö ½«ÍâÉèTIMx¼Ä´æÆ÷ÖØÉèΪȱʡֵ ÊäÈë²ÎÊý TIMx£ºx¿ÉÒÔÊÇ 2,3,4£¬À´Ñ¡ÔñTIMÍâÉè Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ RCC_APB1PeriphResetCmd() ±»µ÷Óú¯Êý RCC_APB2PeriphResetCmd()¡ªT1/T8 Àý£º /* Resets the TIM2 */ TIM_DeInit(TIM2);
º¯ÊýÔÐÍÈçÏ£º
void TIM_DeInit(TIM_TypeDef* TIMx) {
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
//#define IS_TIM_ALL_PERIPH(PERIPH) (((*(u32*)&(PERIPH)) == TIM1_BASE) || ((*(u32*)&(PERIPH)) == TIM2_BASE) || \\ // ((*(u32*)&(PERIPH)) == TIM3_BASE) || ((*(u32*)&(PERIPH)) == TIM4_BASE) || \\ // ((*(u32*)&(PERIPH)) == TIM5_BASE) || ((*(u32*)&(PERIPH)) == TIM6_BASE) || \\ // ((*(u32*)&(PERIPH)) == TIM7_BASE) || ((*(u32*)&(PERIPH)) == TIM8_BASE)) //TIMx_BASEÖµ¶¨ÒåÂÔ¡£
switch (*(u32*)&TIMx) {
case TIM1_BASE:
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);//T1/T8ÔÚAPB2ÖУ¬T2-7ÔÚAPB1ÖÐ RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); //ÏÈÖÃ1£¬ÔÙÇå0 break;
//void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState); //TIMx¸´Î»ÔÚRCC_APB2RSTRºÍRCC_APB1RSTRÖÐ No 1 2 3 4 5 6 u32 RCC_APB2Periph¶¨ÒåÈçÏ£º RCC_ APB2 RSTR¼Ä´æÆ÷¶¨Òå ¶¨ÒåÖµ #define RCC_APB2Periph_AFIO -- #define RCC_APB2Periph_GPIOA #define RCC_APB2Periph_GPIOB #define RCC_APB2Periph_GPIOC #define RCC_APB2Periph_GPIOD ((u32)0x00000001) -- ((u32)0x00000004) ((u32)0x00000008) ((u32)0x00000010) ((u32)0x00000020) ÔÚAPB2 RSTRÖеÄλÖà bit0 £¨±£Áô룩 bit2 bit3 bit4 bit5