set_false_path -from [get_clocks clk_62_5M] -to [get_clocks RX_CLK_125_I1] set_false_path -from [get_clocks clk_62_5M] -to [get_clocks RX_CLK_125_I2]

set_false_path -from [get_clocks RX_CLK_125_I1] -to [get_clocks clk_62_5M] set_false_path -from [get_clocks RX_CLK_125_I2] -to [get_clocks clk_62_5M]

set_false_path -from [get_clocks RX_CLK_1] -to [get_clocks clk_1575] set_false_path -from [get_clocks RX_CLK_1] -to [get_clocks clk_62_5M]

set_false_path -from [get_clocks RX_CLK_2] -to [get_clocks clk_62_5M] set_false_path -from [get_clocks RX_CLK_2] -to [get_clocks clk_1575]

set_false_path -from [get_clocks clk_local_125M] -to [get_clocks clk_1575] #set_false_path -from [get_clocks clk_local_125M] -to [get_clocks clk_62_5M]

#set_false_path -from [get_clocks clk_62_5M] -to [get_clocks clk_mux_125M]

set_ideal_network [get_ports [list RESET clk_50_M clk_1575 ]] set_ideal_network [get_pins fc_ae_1553/clk_mng/RX_CLK_125_I1_buf/Y] set_ideal_network [get_pins fc_ae_1553/clk_mng/RX_CLK_125_I2_buf/Y] set_ideal_network [get_pins fc_ae_1553/clk_mng/clk_local_125M_buf/Y] set_ideal_network [get_pins fc_ae_1553/clk_mux_125M_buf/Y] ################################### # INPUT TIMING # ###################################

set_input_delay 1.2 -clock RX_CLK_125_I1 [get_ports [list RKMSB_E RXD_E]] #set_input_delay 1.2 -clock RX_CLK_125_I2 [get_ports [list RKMSB_E RXD_E]] set_input_delay 3.8 -clock clk_62_5M [get_ports [list Addr_chip ]]

set_input_delay 8.0 -clock clk_1575 [get_ports [list rcva rcvb error sync databus ]]

set_input_delay 2.4 -clock clk_local_125M [get_ports [list PRE1 PRE2 LOOPEN2 PRBSEN2 LOOPEN1 PRBSEN1]]

set_input_delay 8.0 -clock clk_50_M [get_ports [list FRX2_p FRX2_n FRX1_p FRX1_n]]

set_input_delay 3.8 -clock clk_62_5M [get_ports [list DATAa DATAb DATAc ADDR IOEN RD_WR ram_select ]]

################################### # OUTPUT TIMING # ###################################

set_output_delay 3.8 -clock clk_62_5M [get_ports [list INT serdes_out_en]] set_output_delay 3.8 -clock clk_62_5M [get_ports [list DATAa DATAb DATAc RD_WR_sram_A IOEN_sram_A ADDR_sram_A OE_A RD_WR_sram_B IOEN_sram_B ADDR_sram_B OE_B ]]

set_output_delay 8.0 -clock clk_1575 [get_ports [list sync databus odd_even_error

mr r_w_n reg_sam_data cha_n_chb strb_n]]

set_output_delay 2.4 -clock clk_local_125M [get_ports [list TXD_E TKLSB_E TKMSB_E LOOPEN_E PRE_E PRBSEN_E ]]

set_output_delay 8.0 -clock clk_50_M [get_ports [list FTX1_p FTX1_n FTX2_p FTX2_n ]]

################################### # DESIGN AREA # ################################### set_max_area 0

################################### # ENVIRONMENTAL ATTRIBUTES # ###################################

#set_driving_cell -lib_cell DICE_DELAY_DFF_RN -pin Q -library DICE_DELAY_DFF_RN [all_inputs]

#set_drive 0 [list clk_62_5M rst_n] #set_input_transition 0.12 [all_inputs] set_load 10 [all_outputs]

######power optimization########## #set_max_leakage_power 0 #set_max_dynamic_power 0

################################### # Check missing or conflicting #

# constraints # ################################### #check_timing

################################## # Check constraints were correct #

# applied to design # ################################### #report_clock #report_clock -skew #report_port -verbose

################################### # compile & report # ################################### #compile -map_effort medium source

/data/wpei/wpeiwork/zhoulu/zhang/FC_AE_1553_new/v11_inner_ram_DICE_DFF/syn/scripts/netlist.con report_area

report_timing -max_paths 1000 -transition_time -capacitance -loops > report_timing.log

report_timing -max_paths 1000 report_power

report_constraint -all_violators -verbose report_cell

report_compile_options all_connected report_net report_qor

################################### # write compiled design database # ###################################

write -format ddc -hier -o mapped/ddc/asic_top_rst.ddc write -f verilog -h -o mapped/syn_v/asic_top_rst.v write_sdc mapped/sdc/asic_top_rst.sdc write_sdf mapped/sdf/asic_top_rst.sdf quit

template:模板

########################################## # Read design file # ########################################## set active_design seg_drive

read_verilog {encode_seg.v number_mod.v scan.v seg_drive.v}

#ranalyze -format verilog {encode_seg.v number_mod.v scan.v seg_drive.v} #elaborate $active_design current_design $active_design link

############################################## # Design Enverionment # ##############################################

# Operation condition

set_operating_conditions slow set_wire_load_mode enclosed

# Environmental attributes

set_driving_cell -lib_cell DFFHQX4 -pin Q -library slow [all_inputs] set_load [expr 4*[load_of slow/DFFHQX4/D]] [all_outputs]

################################ # Design rule constraint # ################################ set_max_transition 1.8 [current_design] set_max_fanout 10 [current_design]

################################ # Optimization constraint # ################################

# Clock defintion

create_clock -period 2.0 -waveform [list 0.0 1.0] clk #set_dont_touch_netword [list clk ] #set_ideal_network [list clk ] #set_false_path -through rst

# INPUT OUTPUT TIMING

set_input_delay 0.6 -clock clk [all_inputs] #remove_input_delay [get_ports [list clk]] set_output_delay 0.6 -clock clk [all_outputs]

# Design area set_max_area 0

####################################################### # Check missing or conflicting constraints #

####################################################### check_timing

######################################################## # Check constraints were correct applied to design #

######################################################## report_clock

report_clock -skew report_port -verbose

#################################