四、 仿真结果与波形

LAB 8：通过模块间的调用实现自顶向下CPU的是设计

一、 二、

实验目的 实验原理

学习和使用层次化、结构化设计方法。

Verilog HDL中，上层模块引用下层模块与C语言中程序调用有些类似，被引用的子模块在综合时作为其父模块的一部分被综合，形成相应的电路结构。在进行模块实例引用时，必须注意的是模块之间对应的端口，即子模块端口与父模块的内部信号必须是一一对应。

三、 源代码

CPUtest1.dat

//opcode_operand // addr assembly code //-------------- // ---- ----------------------------------------------- @00 111_11110 // 00 BEGIN: JMP TST_JMP

000_00000 // 01 HLT //JMP did not work at all

000_00000 // 02 HLT //JMP did not load PC, it skipped

101_11010 // 03 JMP_OK: LDA DATA_1 001_00000 // 04 SKZ

000_00000 // 05 HLT //SKZ or LDA did not work 101_11011 // 06 LDA DATA_2 001_00000 // 07 SKZ

111_01010 // 08 JMP SKZ_OK

000_00000 // 09 HLT //SKZ or LDA did not work 110_11100 // 0A SKZ_OK: STO TEMP //store non-zero value in TEMP

101_11010 // 0B LDA DATA_1

110_11100 // 0C STO TEMP //store zero value in TEMP 101_11100 // 0D LDA TEMP

001_00000 // 0E SKZ //check to see if STO worked 000_00000 // 0F HLT //STO did not work 100_11011 // 10 XOR DATA_2

001_00000 // 11 SKZ //check to see if XOR worked 111_10100 // 12 JMP XOR_OK

000_00000 // 13 HLT //XOR did not work at all 100_11011 // 14 XOR_OK: XOR DATA_2 001_00000 // 15 SKZ

000_00000 // 16 HLT //XOR did not switch all bits 000_00000 // 17 END: HLT //CONGRATULATIONS - TEST1 PASSED!

111_00000 // 18 JMP BEGIN //run test again

@1A 00000000 // 1A DATA_1: //constant 00(hex) 11111111 // 1B DATA_2: //constant FF(hex)

10101010 // 1C TEMP: //variable - inititially AA(hex)

@1E 111_00011 // 1E TST_JMP: JMP JMP_OK

000_00000 // 1F HLT //JMP is broken

CPUtest2.dat

//opcode_operand // addr assembly code //-------------- // ---- ----------------------------------------------- @00 101_11011 // 00 BEGIN: LDA DATA_2 011_11100 // 01 AND DATA_3 100_11011 // 02 XOR DATA_2 001_00000 // 03 SKZ

000_00000 // 04 HLT //AND doesn't work 010_11010 // 05 ADD DATA_1 001_00000 // 06 SKZ

111_01001 // 07 JMP ADD_OK

000_00000 // 08 HLT //ADD doesn't work 100_11100 // 09 XOR DATA_3

010_11010 // 0A ADD DATA_1 //FF plus 1 makes -1 110_11101 // 0B STO TEMP 101_11010 // 0C LDA DATA_1

010_11101 // 0D ADD TEMP //-1 plus 1 should make zero

001_00000 // 0E SKZ

000_00000 // 0F HLT //ADD Doesn't work

000_00000 // 10 END: HLT //CONGRATULATIONS - TEST2 PASSED!

111_00000 // 11 JMP BEGIN //run test again

@1A 00000001 // 1A DATA_1: //constant 1(hex) 10101010 // 1B DATA_2: //constant AA(hex) 11111111 // 1C DATA_3: //constant FF(hex) 00000000 // 1D TEMP:

CPUtest3.dat

//opcode_operand // addr assembly code //-------------- // ---- ----------------------------------------------------

111_00011 // 00 JMP LOOP //jump to the address of LOOP

@03 101_11011 // 03 LOOP: LDA FN2 //load value in FN2 into accum

110_11100 // 04 STO TEMP //store accumulator in TEMP

010_11010 // 05 ADD FN1 //add value in FN1 to accumulator

110_11011 // 06 STO FN2 //store result in FN2

101_11100 // 07 LDA TEMP //load TEMP into the accumulator

110_11010 // 08 STO FN1 //store accumulator in FN1 100_11101 // 09 XOR LIMIT //compare accumulator to LIMIT

001_00000 // 0A SKZ //if accum = 0, skip to DONE 111_00011 // 0B JMP LOOP //jump to address of LOOP 000_00000 // 0C DONE: HLT //end of program 101_11111 // 0D AGAIN: LDA ONE 110_11010 // 0E STO FN1 101_11110 // 0F LDA ZERO 110_11011 // 10 STO FN2

111_00011 // 11 JMP LOOP //jump to address of LOOP

@1A 00000001 // 1A FN1: //variable - stores 1st Fib. No. 00000000 // 1B FN2: //variable - stores 2nd Fib. No. 00000000 // 1C TEMP: //temporary variable

10010000 // 1D LIMIT: //constant 144 - max value 00000000 // 1E ZERO: //constant 0 00000001 // 1F ONE: //constant 1

CPUtest4.dat 自己编写的CPUtest，实现乘法器

//opcode_operand // addr assembly code //-------------- // ---- ----------------------------------------------------

@03 111_00100 // 03 JMP LOOP //jump to the address of LOOP 101_11011 // 04 LOOP: LDA DATA2 //A=5 010_11010 // 05 ADD DATA1 //A=5+5=10 110_11011 // 06 STO DATA2 //DATA2=10 101_11101 // 07 LDA TIME //A=TIME 011_11111 // 08 AND TIME //A =TIME 010_11100 // O9 ADD TEMP //A=TIME+1 110_11101 // 0A STO TIME //TIME=TIME+1

100_11110 // 0B XOR LIMIT //compare accumulator to LIMIT

001_00000 // 0C SKZ //if accum = 0, skip to DONE 111_00100 // 0D JMP LOOP //jump to address of LOOP 000_00000 // 0E DONE: HLT //end of program

@1A 00000101 // 1A data1: //5 variable - stores 1st Fib. No.