#define FN_2 (0x04) /* fDCOCLK , 2*fNominal */ #define FN_3 (0x08) /* fDCOCLK , 3*fNominal */ #define FN_4 (0x10) /* fDCOCLK , 4.5*fNominal */ #define FN_8 (0x20) /* fDCOCLK , 10*fNominal */ #define FLLD0 (0x40) /* Loop Divider Bit : 0 */ #define FLLD1

#define FLLD_1 */

#define FLLD_2 */

#define FLLD_4 */

#define FLLD_8 8 */

#define SCFI1_ Integrator 1 */

DEFC( SCFI1 #define SCFQCTL_ Control */

DEFC( SCFQCTL (0x80) /* Loop Divider Bit : 1 */ (0x00) /* Multiply Selected Loop Freq. By 1 (0x40) /* Multiply Selected Loop Freq. By 2 (0x80) /* Multiply Selected Loop Freq. By 4 (0xC0) /* Multiply Selected Loop Freq. By (0x0051) /* System Clock Frequency , SCFI1_)

(0x0052) /* System Clock Frequency , SCFQCTL_)

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/* System clock frequency values fMCLK coded with Bits 0-6 in SCFQCTL */ /*

#define

SCFQ_32K

0x00

fMCLK,1*fACLK only a range from */

#define SCFQ_64K (0x01) /* fMCLK,2*fACLK 1+1 to 127+1 is possible */

#define SCFQ_128K fMCLK,4*fACLK */

#define SCFQ_256K fMCLK,8*fACLK */

#define SCFQ_512K fMCLK,16*fACLK */

#define SCFQ_1M fMCLK,32*fACLK */

#define SCFQ_2M fMCLK,64*fACLK */

#define SCFQ_4M fMCLK,128*fACLK */

#define SCFQ_M Disable */

#define FLL_CTL0_ DEFC( FLL_CTL0 (0x03) /* (0x07) /* (0x0F) /* (0x1F) /* (0x3F) /* (0x7F) /* (0x80) /* Modulation (0x0053) /* FLL+ Control 0 */ , FLL_CTL0_)

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#define DCOF (0x01) /* DCO Fault Flag */

#define LFOF (0x02) /* Low Frequency Oscillator Fault Flag */

#define XT1OF (0x04) /* High Frequency Oscillator 1 Fault Flag */

#define XT2OF (0x08) Frequency Oscillator 2 Fault Flag */

#define OSCCAP0 (0x10) Cap 0 */

#define OSCCAP1 (0x20) Cap 1 */

#define XTS_FLL (0x40) high-freq. oscillator */

#define DCOPLUS (0x80) Enable */

#define XCAP0PF (0x00) XOUT Cap = 0pf */

#define XCAP10PF (0x10) XOUT Cap = 10pf */

#define XCAP14PF (0x20) 35

/* High /* XIN/XOUT /* XIN/XOUT /* 1: Selects /* DCO+ /* XIN Cap = /* XIN Cap = /* XIN Cap =

XOUT Cap = 14pf */

#define XCAP18PF (0x30) /* XIN Cap = XOUT Cap = 18pf */

#define FLL_CTL1_ (0x0054) /* FLL+ Control 1 */ DEFC( FLL_CTL1 , FLL_CTL1_)

#define FLL_DIV0 (0x00) /* FLL+ Divide Px.x/ACLK 0 */

#define FLL_DIV1 (0x01) /* FLL+ Divide Px.x/ACLK 1 */

#define SELS (0x04) /* Peripheral Module Clock Source (0: DCO, 1: XT2) */

#define SELM0 (0x08) /* MCLK Source Select 0 */

#define SELM1 (0x10) /* MCLK Source Select 1 */

#define XT2OFF (0x20) /* High Frequency Oscillator 2 (XT2) disable */

#define FLL_DIV_1 (0x00) /* FLL+ Divide Px.x/ACLK By 1 */

#define FLL_DIV_2 (0x01) /* FLL+ Divide

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