250ms \#define

WDT_ADLY_16

(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms \#define

WDT_ADLY_1_9

(WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms \

/* Watchdog mode -> reset after expired time */ /* WDT is clocked by fMCLK (assumed 1MHz) */ #define

WDT_MRST_32

(WDTPW+WDTCNTCL)

/* 32ms interval (default) */

#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms \

#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms \

#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms \

/* WDT is clocked by fACLK (assumed 32KHz) */

#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms \#define

WDT_ARST_250

(WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms

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\#define

WDT_ARST_16

(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms \#define

WDT_ARST_1_9

(WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms \

/* INTERRUPT CONTROL */

/* These two bits are defined in the Special Function Registers */ /* #define WDTIE 0x01 */ /* #define WDTIFG 0x01 */

/************************************************************ * DIGITAL I/O Port1/2

************************************************************/

#define P1IN_ (0x0020) /* Port 1 Input */ READ_ONLY DEFC( P1IN , P1IN_)

#define P1OUT_ (0x0021) /* Port 1 Output */ DEFC( P1OUT , P1OUT_)

#define P1DIR_ (0x0022) /* Port 1 Direction */

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DEFC( P1DIR , P1DIR_)

#define P1IFG_ (0x0023) /* Port 1 Interrupt Flag */ DEFC( P1IFG , P1IFG_)

#define P1IES_ (0x0024) /* Port 1 Interrupt Edge Select */ DEFC( P1IES , P1IES_)

#define P1IE_ DEFC( P1IE #define P1SEL_ DEFC( P1SEL

#define P2IN_ READ_ONLY DEFC( P2IN #define P2OUT_ DEFC( P2OUT #define P2DIR_ DEFC( P2DIR #define P2IFG_ DEFC( P2IFG #define P2IES_ DEFC( P2IES #define P2IE_ DEFC( P2IE (0x0025) /* Port 1 Interrupt Enable */ , P1IE_)

(0x0026) /* Port 1 Selection */ , P1SEL_) (0x0028) /* Port 2 Input */ , P2IN_)

(0x0029) /* Port 2 Output */ , P2OUT_)

(0x002A) /* Port 2 Direction */ , P2DIR_)

(0x002B) /* Port 2 Interrupt Flag */ , P2IFG_)

(0x002C) /* Port 2 Interrupt Edge Select */ , P2IES_)

(0x002D) /* Port 2 Interrupt Enable */ , P2IE_)

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#define P2SEL_ (0x002E) /* Port 2 Selection */ DEFC( P2SEL , P2SEL_)

/************************************************************ * DIGITAL I/O Port3/4

************************************************************/

#define P3IN_ (0x0018) /* Port 3 Input */ READ_ONLY DEFC( P3IN , P3IN_)

#define P3OUT_ (0x0019) /* Port 3 Output */ DEFC( P3OUT , P3OUT_)

#define P3DIR_ (0x001A) /* Port 3 Direction */ DEFC( P3DIR , P3DIR_)

#define P3SEL_ (0x001B) /* Port 3 Selection */ DEFC( P3SEL , P3SEL_)

#define P4IN_ (0x001C) /* Port 4 Input */ READ_ONLY DEFC( P4IN , P4IN_)

#define P4OUT_ (0x001D) /* Port 4 Output */ DEFC( P4OUT , P4OUT_)

#define P4DIR_ (0x001E) /* Port 4 Direction */ DEFC( P4DIR , P4DIR_)

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