Double-click the To cell, click the arrow that appears on the right side of the cell, and click Select Assignment Group to enter an existing assignment group name.
4. To specify an assignment source, repeat step 3 to specify the source name in the
From cell.
5. In the spreadsheet, double-click the Assignment Name cell and select the timing
assignment you wish to make.
6. For assignments that require a value, double-click the Value cell and type or select
the appropriate assignment value.
To specify timing analysis reporting restrictions: 1. On the Assignments menu, click Settings.
2. In the Category list, double-click Timing Analysis Settings. 3. Click Timing Analyzer Reporting.
4. To specify the range of timing analysis information reported, specify one or more
options in the Timing Analyzer Reporting page. 5. Click OK.
(2)说明其中的Compilation Process的功能和使用方法。 Compilation Process Settings Page (Settings Dialog Box)
Allows you to direct the Compiler to use smart compilation, save synthesis results for the current design's top-level entity, disable the OpenCore Plus hardware evaluation feature, or export version-compatible database files. You can also control the amount of disk space used for compilation.
Use Smart compilation:
Preserve fewer node names to save disk space: Run Assembler during compilation:
Save a node-level netlist of the entire design into a persistent source file: Export version-compatible database: Display entity name for node name:
Disable OpenCore Plus hardware evaluation feature: (3)说明Analysis&Synthesis Setting的功能和使用方法，以及其中的Synthesis Netlist Optimization的功能和使用方法。
Analysis & Synthesis Settings Page (Settings Dialog Box) Allows you to specify options for logic synthesis. Create debugging nodes for IP cores: More Settings: Other options: Message Level: Advanced:
Synthesis Netlist Optimizations Page (Settings Dialog Box)
Specifies the following options for optimizing netlists during synthesis: Perform WYSIWYG primitive resynthesis: Perform gate-level register retiming:
Allow register retiming to trade off Tsu/Tco with Fmax:
?
4-3 概述Assignments菜单中Assignment Editor的功能，举例说明。
About the Assignment Editor
User Interface and Functionality: Customizing the User Interface: Pin Information:
LogicLock Assignments:
Assignment Validation and Output: Integration with the Pin Planner:
4-4 全程编译主要包括哪几个功能模块?这些功能模块各有什么作用?P99~101
4-5 有哪三种引脚锁定的方法?详细说明这三种方法的使用流程和注意事项，并说明它们各自的特点。提示，第三种方法是选择Assignments中的Pins对话框，进行引脚设置。P103~105 4-6 详细说明通过JTAG口对FPGA的配置Flash EPCS器件的间接编程方法和流程。P106~107
4-7 对第3章的习题3-13和习题3-14的设计结果，用本章介绍的方法，分别在QuartusⅡ上进行仿真，验证其正确性；然后在EP3C55芯片中进行硬件测试和验证。
--3-13 4位移位相加型乘法器设计(例化调用加法器) LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY MULT4B IS
GENERIC( S: INTEGER:=4); --定义参数S为整数类型，且等于4 PORT( R: OUT STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); A,B: IN STD_LOGIC_VECTOR(S-1 DOWNTO 0)); END ENTITY MULT4B;
ARCHITECTURE ONE OF MULT4B IS COMPONENT addern IS
PORT(a,b: IN STD_LOGIC_VECTOR; result: out STD_LOGIC_VECTOR); END COMPONENT;
SIGNAL A0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0);
SIGNAL RR3,RR2,RR1,RR0,ZZ1,ZZ0: STD_LOGIC_VECTOR(2*S-1 DOWNTO 0); BEGIN
A0<=CONV_STD_LOGIC_VECTOR(0,S) & A; PROCESS(A,B) BEGIN
IF(B(0)='1')THEN RR0<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 0);ELSE RR0<=(OTHERS=>'0');END IF; IF(B(1)='1')THEN RR1<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 1);ELSE RR1<=(OTHERS=>'0');END IF; IF(B(2)='1')THEN RR2<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 2);ELSE RR2<=(OTHERS=>'0');END IF; IF(B(3)='1')THEN RR3<=TO_STDLOGICVECTOR(TO_BITVECTOR(A0) SLL 3);ELSE RR3<=(OTHERS=>'0');END IF; END PROCESS;
u0: addern PORT MAP(a=>RR0,b=>RR1,result=>ZZ0); u1: addern PORT MAP(a=>ZZ0,b=>RR2,result=>ZZ1); u2: addern PORT MAP(a=>ZZ1,b=>RR3,result=>R); END ARCHITECTURE ONE;
--解：3-14 用循环语句设计一个7人投票表决器，及一个4位4输出最大数值检测电路。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vote_7 IS
PORT( DIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);--7位表决输入(1:同意，0:不同意) G_4: OUT STD_LOGIC; --超过半数指示 CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));--表决结果统计数 END vote_7;
ARCHITECTURE BHV OF vote_7 IS BEGIN
PROCESS(DIN)
VARIABLE Q: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN Q:=\
FOR n IN 0 TO 6 LOOP -- n是LOOP的循环变量 IF(DIN(n)='1') THEN Q:=Q+1; END IF; END LOOP; CNTH<=Q;
IF Q>=4 THEN G_4<='1'; ELSE G_4<='0'; END IF; END PROCESS; END BHV;
4-8 如果对于一个设计项目，如全加器进行全程编译，假设已将信号端口cout和sum分别锁定于引脚Dl和K22，编译后发现Quartus II给出编译报错：“Can't place multiple pins
assigned to pin Location Pin D1(或K22)”，试问，问题出在哪里?如何解决?P99
提示：考虑可能这些引脚具有双功能。选择图4-5所示窗口中的双目标端口设置页，如将nCEO原来的“Use as programming pin”改为“Use as regular I/O”。这样可以将此端口也作普通I/O口来用。 4-9 用74148（8-3线八进位优先编码器）和与非门实现8421BCD优先编码器。用3片74139（2线-4线译码器）组成一个5-24线译码器。
解：用74148（8-3线八进位优先编码器）和与非门实现8421BCD优先编码器。
解：用3片74139（2线-4线译码器）组成一个5-24线译码器。
4-10 用74283（4位二进制全加器）加法器和逻辑门设计实现一位8421BCD码加法器电路，输入输出均是BCD码，CI为低位的进位信号，CO为高位的进位信号，输入为两个1位十进制数A，输出用S表示。(化简)
解：用74283（4位二进制全加器）加法器和逻辑门设计实现一位8421BCD码加法器电路。
解：用74283（4位二进制全加器）加法器和逻辑门设计实现一位8421BCD码加法器电路（化简）。
4-11 用原理图输入方式设计一个7人表决电路（用4位二进制全加器），参加表决者7人，同意为1，不同意为0，同意者过半则表决通过，绿指示灯亮；表决不通过则红指示灯亮。 解：用原理图输入方式设计一个7人表决电路
4-12 在本章示例中，或自主选择一个示例，使用keep属性，说明keep属性应用的好处。P112
4-13 在本章示例中，或自主选择一个示例，使用SignalProbe在EP3C55上进行硬件测试，