PROCESS(A,B) BEGIN

IF (AB) THEN GT<='1';ELSE GT<='0';END IF; IF (A=B) THEN EQ<='1';ELSE EQ<='0';END IF; END PROCESS;

END ARCHITECTURE ONE;

--3-22 ±È½ÏÆ÷µÄÊäÈëÊÇÁ½¸ö´ý±È½ÏµÄ8λÊýA=[A7..A0]ºÍB=[B7..80]£¬Êä³öÊÇEQ¡¢GT¡¢F¡£µ±A=BʱEQ=1£»µ±A>BʱGT=1£»µ±A

--µÚ¶þÖÖÉè¼Æ·½°¸ÊÇÀûÓüõ·¨Æ÷À´Íê³É£¬Í¨¹ý¼õ·¨ÔËËãºóµÄ·ûºÅºÍ½á¹ûÀ´ÅбðÁ½¸ö±»±È½ÏÖµµÄ´óС¡£

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COMP IS

PORT( A,B: IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Á½¸ö3λÊäÈë LT: OUT STD_LOGIC; --СÓÚÊä³ö GT: OUT STD_LOGIC; --´óÓÚÊä³ö EQ: OUT STD_LOGIC); --µÈÓÚÊä³ö END ENTITY COMP;

ARCHITECTURE ONE OF COMP IS

SIGNAL C: STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL D,E,F,G: INTEGER RANGE 255 DOWNTO 0; BEGIN C<=A-B;

D<=10;

E<=16#D9#; F<=8#72#;

G<=2#11010010#; PROCESS(A,B) BEGIN

IF (C(7)='1') THEN LT<='1';ELSE LT<='0';END IF; IF (C=0) THEN EQ<='1'; ELSE EQ<='0';

IF(C(7)='0')THEN GT<='1';ELSE GT<='0';END IF; END IF;

END PROCESS;

END ARCHITECTURE ONE;

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--½â1£º²ã´ÎÀý»¯¡£µ×²ãÔª¼þmux21a.vhd³ÌÐòÈçÏ£º LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21a IS

PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux21a;

ARCHITECTURE one OF mux21a IS BEGIN

PROCESS(a,b,s) BEGIN

IF s='0' THEN y<=a; ELSE y<=b; END IF;

END PROCESS;

END ARCHITECTURE one;

--½â1£º²ã´ÎÀý»¯¡£¶¥²ãmux41b.vhd³ÌÐòÈçÏ£º LIBRARY ieee;

USE ieee.std_logic_1164.all; ENTITY mux41b IS

port(X0,X1,X2,X3: IN STD_LOGIC; S0,S1: IN STD_LOGIC; OUTY: OUT STD_LOGIC); END mux41b;

ARCHITECTURE bdf_type OF mux41b IS component mux21a

PORT(a,b,s: IN STD_LOGIC; y: OUT STD_LOGIC); end component;

signal N0,N1: STD_LOGIC; BEGIN

u1: mux21a PORT MAP(a=>X0,b=>X1,s=>S0,y=>N0); u2: mux21a PORT MAP(a=>X2,b=>X3,s=>S0,y=>N1); u3: mux21a PORT MAP(a=>N0,b=>N1,s=>S1,y=>OUTY); END;

--½â2£ºµ¥²ã½á¹¹mux41a.vhd³ÌÐòÈçÏ£º LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS

PORT(x1,x2,x3,x4,s0,s1: IN STD_LOGIC; y: OUT STD_LOGIC); END ENTITY mux41a;

ARCHITECTURE one OF mux41a IS signal N0,N1: STD_LOGIC; BEGIN

com1: PROCESS(x1,x2,s0) BEGIN

IF s0='0' THEN N0<=x1; ELSE

N0<=x2; END IF;

END PROCESS;

com2: PROCESS(x3,x4,s0) BEGIN

IF s0='0' THEN N1<=x3; ELSE

N1<=x4; END IF;

END PROCESS;

com3: PROCESS(N0,N1,s1) BEGIN

IF s1='0' THEN y<=N0; ELSE y<=N1; END IF;

END PROCESS;

END ARCHITECTURE one;

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4-1 ¹éÄÉÀûÓÃQuartus II½øÐÐVHDLÎı¾ÊäÈëÉè¼ÆµÄÁ÷³Ì£º´ÓÎļþÊäÈëÒ»Ö±µ½Ó²¼þ¹¦ÄܲâÊÔ¡£P96~P110

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4-2 ²Î¿¼Quartus IIµÄHelp£¬Ïêϸ˵Ã÷Assignments²Ëµ¥ÖÐSettings¶Ô»°¿òµÄ¹¦ÄÜ¡£ £¨1£©ËµÃ÷ÆäÖеÄTiming Requirements & QptionsµÄ¹¦ÄÜ¡¢Ê¹Ó÷½·¨ºÍ¼ì²â;¾¶¡£ £¨2£©ËµÃ÷ÆäÖеÄCompilation ProcessµÄ¹¦ÄܺÍʹÓ÷½·¨¡£

£¨3£©ËµÃ÷Analysis & Synthesis SettingµÄ¹¦ÄܺÍʹÓ÷½·¨£¬ÒÔ¼°ÆäÖеÄSynthesis Netlist OptimizationµÄ¹¦ÄܺÍʹÓ÷½·¨¡£

(1)˵Ã÷ÆäÖеÄTiming Requirements&QptionsµÄ¹¦ÄÜ¡¢ËûÓ÷½·¨ºÍ¼ì²â;¾­¡£ Specifying Timing Requirements and Options (Classic Timing Analyzer)

You can specify timing requirements for Classic timing analysis that help you achieve the desired speed performance and other timing characteristics for the entire project, for specific design entities, or for individual clocks, nodes, and pins.

When you specify either project-wide or individual timing requirements, the Fitter optimizes the placement of logic in the device in order to meet your timing goals.

You can use the Timing wizard or the Timing Analysis Settings command to easily specify all project-wide timing requirements, or you can use the Assignment Editor to assign individual clock or I/O timing requirements to specific entities, nodes, and pins, or to all valid nodes included in a wildcard or assignment group assignment. To specify project-wide timing requirements:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings.

3. To specify project-wide tSU, tH, tCO, and/or tPD timing requirements, specify values

under Delay requirements.

4. To specify project-wide minimum delay requirements, specify options under

Minimum delay requirements.

5. Under Clock Settings, select Default required fmax.

6. In the Default required fmax box, type the value of the required fMAX and select a time

unit from the list.

7. If you want to specify options for cutting or reporting certain types of timing paths

globally, enabling recovery/removal analysis, enabling clock latency, and reporting unconstrained timing paths, follow these steps: 8. Click OK.

To specify clock settings:

1. On the Assignments menu, click Settings.

2. In the Category list, select Timing Analysis Settings. 3. Under Clock Settings, click Individual Clocks. 4. Click New.

5. In the New Clock Settings dialog box, type a name for the new clock settings in the

Clock settings name box.

6. To assign the clock settings to a clock signal in the design, type a clock node name in

the Applies to node box, or click Browse... to select a node name using the Node Finder.

7. If you want to specify timing requirements for an absolute clock, follow these steps: 8. If you have already specified timing requirements for an absolute clock, and you want

to specify timing requirements for a derived clock, follow these steps: 9. In the New Clock Settings dialog box, click OK. 10. In the Individual Clocks dialog box, click OK. 11. In the Settings dialog box, click OK. To specify individual timing requirements:

1. On the Assignments menu, click Assignment Editor.

2. In the Category bar, select Timing to indicate the category of assignment you wish to

make.

3. In the spreadsheet, select the To cell and perform one of the following steps:

? Type a node name and/or wildcard that identifies the destination node(s) you

want to assign.

? Double-click the To cell and click Node Finder to use the Node Finder to enter

a node name.