xin yin

a

c

b

diff_out

图3-18 全减器结构图

--解(1.1)：实现1位半减器h_suber(diff=x-y；s_out=1,x

PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber;

ARCHITECTURE hs1 OF h_suber IS BEGIN

Diff <= x XOR (NOT y); s_out <= (NOT x) AND y;

END ARCHITECTURE hs1;

--解(1.2)：采用例化实现图4-20的1位全减器

LIBRARY IEEE; --1位二进制全减器顺层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS

PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END ENTITY f_suber;

ARCHITECTURE fs1 OF f_suber IS

COMPONENT h_suber --调用半减器声明语句 PORT(x, y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END COMPONENT;

SIGNAL a,b,c: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN

u1: h_suber PORT MAP(x=>xin,y=>yin, diff=>a, s_out=>b); u2: h_suber PORT MAP(x=>a, y=>sub_in, diff=>diff_out,s_out=>c); sub_out <= c OR b;

END ARCHITECTURE fs1;

(2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。

x7 y7 a6 x1 y1 xin sub_out yin u7 sub_in diff_out ………………. ………………. xin sub_out yin u1 sub_in diff_out xin sub_out yin u0 sub_in diff_out 串行借位的8位减法器

a1 sout diff7

a0 diff1 diff0

x0 y0 sin

--解(2)：采用例化方法，以1位全减器为基本硬件；实现串行借位的8位减法器(上图所示)。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber_8 IS

PORT(x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC; y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_LOGIC; diff0,diff1,diff2,diff3: OUT STD_LOGIC; diff4,diff5,diff6,diff7,sout: OUT STD_LOGIC); END ENTITY suber_8;

ARCHITECTURE s8 OF suber_8 IS

COMPONENT f_suber --调用全减器声明语句 PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END COMPONENT;

SIGNAL a0,a1,a2,a3,a4,a5,a6: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN

u0:f_suber PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0); u1:f_suber PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1); u2:f_suber PORT MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2); u3:f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3); u4:f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4); u5:f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5); u6:f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6); u7:f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout); END ARCHITECTURE s8;

3-5 用VHDL设计一个3-8译码器，要求分别用(条件)赋值语句、case语句、if else语句或移位操作符来完成。比较这4种方式中，哪一种最节省逻辑资源。 解（1）：条件赋值语句

--3-5 3到8译码器设计(条件赋值语句实现)

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。 ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

WITH CONV_INTEGER(DIN) SELECT DOUT<=\ \ \ \ \ \ \ \

UNAFFECTED WHEN OTHERS; END behave; 解（2）：case语句

--3-5 3到8译码器设计(case语句实现) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。 ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

PROCESS (DIN) BEGIN

CASE CONV_INTEGER(DIN) IS WHEN 0 => DOUT<=\ WHEN 1 => DOUT<=\ WHEN 2 => DOUT<=\ WHEN 3 => DOUT<=\ WHEN 4 => DOUT<=\ WHEN 5 => DOUT<=\ WHEN 6 => DOUT<=\ WHEN 7 => DOUT<=\ WHEN OTHERS => NULL; END CASE;

END PROCESS; END behave; 解（3）：if_else语句

--3-5 3到8译码器设计(if_else语句实现) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。 ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

PROCESS (DIN) BEGIN

IF CONV_INTEGER(DIN)=0 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=1 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=2 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=3 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=4 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=5 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=6 THEN DOUT<=\ ELSIF CONV_INTEGER(DIN)=7 THEN DOUT<=\ END IF;

END PROCESS; END behave; 解（4）：移位操作符

--3-5 3到8译码器设计(移位操作实现) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; --为使用类型转换函数，打开此程序包。 ENTITY decoder3to8 IS

port( DIN: IN STD_LOGIC_VECTOR(2 DOWNTO 0); DOUT: OUT BIT_VECTOR(7 DOWNTO 0)); END decoder3to8;

ARCHITECTURE behave OF decoder3to8 IS BEGIN

DOUT<=\被移位部分是常数 END behave;

3-6 设计一个比较电路，当输入的8421BCD码大于5时输出1，否则输出0。 --解：3-6 设计一个比较电路，当输入的8421BCD码大于5时输出1，否则输出0。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;