½â(2)£ºÓÃVHDLÉè¼Æ²úÉú01001011001ÐòÁÐ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY S_generator IS
PORT(CLK,CLR: IN STD_LOGIC; --¹¤×÷ʱÖÓ/¸´Î»ÐźŠS_out: OUT STD_LOGIC);--ÐòÁÐÊä³öλ END S_generator;
ARCHITECTURE behav OF S_generator IS
SIGNAL D: STD_LOGIC_VECTOR(10 DOWNTO 0);--11λѻ·ÒÆÎ»¼Ä´æÆ÷ BEGIN
PROCESS(CLK,CLR) BEGIN
IF CLK'EVENT AND CLK='1' THEN --ʱÖÓµ½À´Ê±£¬Öðλ×óÒÆÑ»·Êä³öÐòÁÐλ IF CLR='1' THEN D<=\¸´Î»²Ù×÷£¬²úÉú11λ´ýÊä³öÐòÁÐ ELSE
D(10 DOWNTO 1)<=D(9 DOWNTO 0); D(0)<=D(10); S_out<=D(10); END IF; END IF; END PROCESS; END behav;
½â(3£º)ÓÃÔÀíͼÉè¼ÆÇÒ¿ÉÔ¤ÖÃÊýµÄ11λÐòÁÐ
8-7 ½«Àý8-11(ÓûÉè¼Æ4Ñ¡1Èý̬×ÜÏß)ÖеÄËĸöIFÓï¾ä·Ö±ðÓÃËĸö²¢Áнø³ÌÓï¾ä±í´ï³öÀ´¡£
--8-7 Ð޸ġ¾Àý8-11¡¿(ÓûÉè¼Æ4Ñ¡1Èý̬×ÜÏß)£¬ÓÃ4¸ö½ø³ÌÉè¼Æ4Ñ¡1ͨµÀÈý̬×ÜÏß(8λ)µç· LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY tristate2 IS
port(input3,input2,input1,input0 :
IN STD_LOGIC_VECTOR(7 DOWNTO 0); enable : IN STD_LOGIC_VECTOR(1 DOWNTO 0); output : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ENTITY tristate2 ;
ARCHITECTURE multiple_drivers OF tristate2 IS BEGIN
COM3: PROCESS(enable,input3) BEGIN
IF enable=\ END PROCESS;
COM2: PROCESS(enable,input2) BEGIN
IF enable=\ END PROCESS;
COM1: PROCESS(enable,input1) BEGIN
IF enable=\ END PROCESS;
COM0: PROCESS(enable,input0) BEGIN
IF enable=\ END PROCESS;
END ARCHITECTURE multiple_drivers;
10 ϰ Ìâ
10-1 ¾Ù¶þÀý˵Ã÷£¬ÓÐÄÄЩ³£ÓÃʱÐòµç·ÊÇ״̬»ú±È½ÏµäÐ͵ÄÌØÊâÐÎʽ£¬²¢ËµÃ÷ËüÃÇÊôÓÚʲôÀàÐ͵Ä״̬»ú(±àÂëÀàÐÍ¡¢Ê±ÐòÀàÐͺͽṹÀàÐÍ)¡££¨Ìáʾ£º¶þ½øÖƼÆÊýÆ÷¡¢¡°00000001¡±×óÑ»·ÒÆÎ»¼Ä´æÆ÷£©
½â£º1£©¶þ½øÖƼÆÊýÆ÷¡¢Ñ»·ÒÆÎ»¼Ä´æÆ÷¡£
2£©¶þ½øÖƼÆÊýÆ÷£ºMooreÐÍ״̬»ú£»Ë³Ðò±àÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ 3£©¡°00000001¡±×óÑ»·ÒÆÎ»¼Ä´æÆ÷£ºMooreÐÍ״̬»ú£»Ò»Î»ÈÈÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£
--(1)¼ÆÊýÆ÷£ºMooreÐÍ״̬»ú£»Ë³Ðò±àÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC); END COUNT;
ARCHITECTURE behav OF COUNT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15); type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(3 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --ʱÐò×éºÏÖ÷¿Ø½ø³Ì£¬´Î̬ת»» IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s8; WHEN s8 => cs<=s9; WHEN s9 => cs<=s10; WHEN s10=> cs<=s11; WHEN s11=> cs<=s12; WHEN s12=> cs<=s13; WHEN s13=> cs<=s14; WHEN s14=> cs<=s15; WHEN s15=> cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF;
IF cs=s15 then COUT<='1'; else COUT<='0'; END IF; END PROCESS;
Q<=val_arr_STATE(cs); END behav;
--(2)\×óÑ»·ÒÆÎ»¼Ä´æÆ÷£ºMooreÐÍ״̬»ú£»Ò»Î»ÈÈÂ룻״̬±àÂëÖ±½ÓÊä³ö¡£ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY LEFT_SHIFT IS
PORT(CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); Cy: OUT STD_LOGIC); END LEFT_SHIFT;
ARCHITECTURE behav OF LEFT_SHIFT IS
type STATE is(s0,s1,s2,s3,s4,s5,s6,s7);
type arr_STATE is array(STATE) of STD_LOGIC_VECTOR(7 DOWNTO 0);
constant val_arr_STATE: arr_STATE:=(\ \
SIGNAL cs: STATE; BEGIN
PROCESS(cs)
BEGIN --ʱÐò×éºÏÖ÷¿Ø½ø³Ì£¬´Î̬ת»» IF CLK'EVENT AND CLK='1' THEN CASE cs IS
WHEN s0 => cs<=s1; WHEN s1 => cs<=s2; WHEN s2 => cs<=s3; WHEN s3 => cs<=s4; WHEN s4 => cs<=s5; WHEN s5 => cs<=s6; WHEN s6 => cs<=s7; WHEN s7 => cs<=s0; WHEN OTHERS=> cs<=s0; END CASE; END IF; END PROCESS;
Q<=val_arr_STATE(cs); Cy<=val_arr_STATE(cs)(7); END behav;
10-2 ÐÞ¸ÄÀý10-1£¬½«ÆäÖ÷¿Ø×éºÏ½ø³Ì·Ö½âΪÁ½¸ö½ø³Ì£¬Ò»¸ö¸ºÔð״̬ת»»£¬ÁíÒ»¸ö¸ºÔðÊä³ö¿ØÖÆÐźš£
--10-2 ÐÞ¸ÄÀý10-1£¬½«ÆäÖ÷¿Ø×éºÏ½ø³Ì·Ö½âΪÁ½¸ö½ø³Ì£¬Ò»¸ö¸ºÔð״̬ת»»£¬ÁíÒ»¸ö¸ºÔðÊä³ö¿ØÖÆÐźš£ LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS
PORT(clk,reset : IN STD_LOGIC;--Ö÷¿ØÊ±Ðò½ø³ÌʱÖÓÇý¶¯ºÍ¸´Î»ÐźÅ