state <=w01;wireout<='0';
elsif (flag = 34 ) then flag:=35;state <=w0; elsif (flag = 35 ) then flag:=36;
state <=w01;wireout<='0';
--第二次写完,跳到s7,直接开始读数据
elsif (flag = 36 ) then flag:=40;state <=s7; end if;
when s6 => reset<='0';
if (i = 750000 or wireout='1' ) then --延时750ms!!!! state <= s0;reset<='1'; --跳回s0,再次初始化 end if;
when s7 => --读数据 if(flag = 40 ) then flag:=41;
state <=read0;light:=0; wireout<='0';
elsif (flag = 41 ) then flag:=42;
state <=read0;light:=1; wireout<='0';
elsif (flag = 42 ) then flag:=43;
state <=read0;light:=2; wireout<='0';
elsif (flag = 43 ) then flag:=44;
state <=read0;light:=3; wireout<='0';
elsif (flag = 44 ) then flag:=45;
state <=read0;light:=4; wireout<='0';
elsif (flag = 45 ) then flag:=46;
state <=read0;light:=5; wireout<='0';
elsif (flag = 46 ) then flag:=47;
state <=read0;light:=6; wireout<='0';
elsif (flag = 47 ) then flag:=48;
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state <=read0;light:=7; wireout<='0';
elsif (flag = 48 ) then flag:=49;
state <=read0;light:=8; wireout<='0';
elsif (flag = 49 ) then flag:=50;
state <=read0;light:=9; wireout<='0';
elsif (flag = 50 ) then flag:=51;
state <=read0;light:=10;wireout<='0';
elsif (flag = 51 ) then flag:=52;
state <=read0;light:=11;wireout<='0';
elsif (flag = 52 ) then flag:=53;
state <=read0;light:=12;wireout<='0';
elsif (flag = 53 ) then flag:=54;
state <=read0;light:=13;wireout<='0';
elsif (flag = 54 ) then flag:=55;
state <=read0;light:=14;wireout<='0';
elsif (flag = 55 ) then flag:=60;
state <=read0;light:=15;wireout<='0';
elsif (flag = 60 ) then flag:=0;state<=s0; end if;
when w0 => wireout<='0'; --输出0 reset<='0';
if (i = 80) then --延时80us wireout<='Z'; --释放总线，自动拉高 reset<='1';state<=w00; end if;
when w00 => state<=s5; --空状态 when w01=> state<=w1; --空状态
when w1 => wireout<='Z'; --输出1释放总线，自动拉高
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reset<='0';
if (i = 80) then --延时80us reset<='1';state<=s5; end if;
when read0=> state <= read1; --空延时状态
when read1=> wireout <= 'Z'; --释放总线 reset<='0';
if (i = 10) then --再延时10us reset<='1';state <= read2; end if;
when others =>state <=s00; end case; end if; end process;
process(clk,reset) begin
if (reset='1')then i<=0;
elsif rising_edge(clk) then i<=i+1; end if;
end process; end architecture init;
8.2 液晶显示程序
library ieee;
use IEEE.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity lcd1602 is
port(clk, reset: in std_logic;
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LCD_Data: out std_logic_vector(8 downto 0); en: out std_logic; rw: out std_logic);
end lcd1602;
architecture gongneng of lcd1602 is signal LCD_Clk: std_logic;
signal s : integer range 0 to 10000000; begin
--50MHz to 5Hz process(clk, reset) begin
if reset = '0' then LCD_Clk <= '0';
s <= 0;
elsif clk'event and clk = '1' then
if s = 10000000 then
s <= 0;
LCD_Clk <= not LCD_Clk;
else
s <= s + 1;
end if; end if; end process;
rw <='0'; en <= LCD_Clk; process(LCD_Clk)
variable cnt: std_logic_vector(4 downto 0):=\
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