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spru131g TMS320C54x DSP Reference Set Volume 1 CPU and Peripherals
Carry is set to 1 if the result of an addition generates a carry; it is cleared to 0 if the result of a subtraction generates a borrow. Otherwise, it is reset after an addition and it is set after a subtraction, except for an ADD or SUB with a 16-bit shift. In these cases, the ADD can only set and the SUB only reset the carry bit, but they cannot affect it otherwise. Carry and borrow are defined at the 32nd bit position and are operated at the ALU level only. The shift and rotate instructions (ROR, ROL, SFTA, and SFTL), and the MIN, MAX, ABS, and NEG instructions also affect this bit.
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ÔÙÀ´¿´µÚ12λ TC Test/control flag λ ¸´Î»ÖµÎª1 ¾ÍÊǸù¾ÝÆä״̬À´¿ØÖƳÌÐòµÄ×ßÏòµÄ
Test/control flag. TC stores the results of the arithmetic logic unit (ALU) test bit op- erations. TC is affected by the BIT, BITF, BITT, CMPM, CMPR, CMPS, and SFTC instructions. The status (set or cleared) of TC determines if the conditional branch, call, execute, and return instructions execute. TC = 1 if the following conditions are true: A bit tested by BIT or BITT is a 1.
A compare condition tested by CMPM, CMPR, or CMPS exists between a data- memory value and an immediate operand, AR0 and another auxiliary register, or an accumulator high word and an accumulator low word.
Bit 31 and bit 30 of an accumulator tested by SFTC have different values from each other.
ÔÙÀ´¿´13λµ½15λ ARP Auxiliary register pointer¸´Î»ÖµÎª000
Auxiliary register pointer. This 3-bit field selects the auxiliary register to use in the com- patibility mode of indirect single-operand addressing (see section 5.5, Indirect Ad- dressing, page 5-10). ARP must always be set to zero when the DSP is in standard mode (CMPT = 0).
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3.3.4.6 Auxiliary Registers (AR0¨CAR7)
The eight 16-bit auxiliary registers (AR0¨CAR7) can be accessed by the CPU and modified by the auxiliary register arithmetic units (ARAUs). The primary function of the auxiliary registers is to generate 16-bit addresses for data space. However, these registers can also act as general-purpose registers or counters. For information about the role the auxiliary registers play in data- memory addressing, see section 5.5, Indirect Addressing, on page 5-10.
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ractional mode. When FRCT is 1, the multiplier output is left-shifted by one bit to compensate for an extra sign bit
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µÚ12λ HM ¸´Î»ÖµÎª0 Hold mode.
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XF status. XF indicates the status of the external flag (XF) pin, which is a general- purpose output pin. The SSBX instruction can set XF and the RSBX instruction can reset XF.
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MP/MC Microprocessor/microcomputer mode. À´Ô´ÓÚÒý½Å OVLY RAM overlay
AVIS Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins
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OVLY = 0 The on-chip RAM is addressable in data space but not inprogram space.
OVLY = 1 The on-chip RAM is mapped into program space and data space.Data page 0 (addresses 0h to 7Fh), however, is not mapped intoprogram space.
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