基于VerilogHDL语言的串å�£è®¾è®¡è¯´æ˜?- 百度文库 ÏÂÔØ±¾ÎÄ

.

endmodule

ΪÁ˲âÊÔÊÕ·¢ÊÇ·ñÕý³££¬Ð´µÄTest Bench

`timescale 1ns/1ns module trsb;

reg clk,rst,en; reg [7:0]TxD_data; reg [2:0]Wsec;

wire TxD,TxD_busy,rcven; wire [7:0]RxD_data; trans trsb(.clk(clk), .rst(rst), .en(en), .TxD(TxD), .Wsec(Wsec),

.TxD_busy(TxD_busy), .TxD_data(TxD_data), .rcven(rcven),

.RxD_data(RxD_data), .RxD(TxD) ); initial begin en = 0;

TxD_data = 0; rst = 1; #1 Wsec=2; #54 rst=0; #70 rst=1;

#10 TxD_data = 8'b11011001; #10 en = 1'b1;

#1250000 en = 1'b1;

end initial begin

#3790000 TxD_data = 8'b01011010; #10 en = 1'b1;

#2750000 en = 1'b0;

#1290000 TxD_data = 8'b101001010; #10 en = 1'b1;

#2750000 en = 1'b0;

. . .

.

end

initial begin clk = 1; while (1)

#10 clk = ~clk; end

endmodule

FPGAʵÏÖ´®ÐÐ½Ó¿Ú RS232(1) 2008-12-17 11:38

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FPGAʵÏÖ´®ÐÐ½Ó¿Ú RS232(2) 2008-12-17 11:39

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Ö»ÐèÒª½« 1.8432MHz 16·ÖƵ±ã¿ÉµÃµ½ 115200HzµÄʱÖÓ£¬¶à·½±ã°¡£¡ reg [3:0] BaudDivCnt;

always (posedge clk) BaudDivCnt <= BaudDivCnt + 1; wire BaudTick = (BaudDivCnt==15);

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