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基于Verilog HDL语言的串口设计
串口Verilog HDL代码： //串口 module
trans(clk,rst,en,TxD_data,Wsec,RxD,TxD,TxD_busy,rcven,RxD_data);//时钟50MHz
input clk,rst,en; //en时发送数据使能 input [7:0]TxD_data; //发送数据输入
input [2:0]Wsec; //波特率调节0-2400；1-4800；2-9600；3-14400；4-19200；5-38400；6-115200；7-128000 input RxD; //接收数据输入端
output TxD,TxD_busy,rcven;//发送，发送忙，接收结束标志输出 output [7:0]RxD_data;//接收数据输出
wire Baud1,Baud8;
reg [7:0]addwire;//RAM地址连线 reg [7:0]data;
wire[7:0]AD_t;//读取RAM数据的地址用于发送 wire[7:0]AD_r;//接收的数据存储在RAM中的地址 wire [7:0]datawire;//数据连线 //发送例化 trans_t
tt1(.clk_t(clk),.rst_t(rst),.en_t(en),.BTI_t(Baud1),.recen(recen),
.TxD_data_t(datawire),.TxD_t(TxD),.addro_t(AD_t),.TxD_busy_t(TxD_busy));
//波特生成例化 BaudG
tt2(.clk_b(clk),.rst_b(rst),.BTO_b(Baud1),.BTO_R(Baud8),.Wsec_b(Wsec));
//接收例化
trans_r tt3(.clk_r(clk),.rst_r(rst),.BTI_r(Baud8),.RxD_r(RxD),
.RxD_data_r(RxD_data),.wren_r(wren_r),.addro_r(AD_r),.RxD_end(RxD_end));
//LPM_RAM例化 RAM0
tt4(.address(addwire),.clock(~clk),.data(data),.wren(wren_r),.q(datawire));
always (posedge clk or negedge rst)
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if(~rst)
addwire <= 8'b00000000; else if(RxD_end) begin
addwire <=AD_r ;data<=RxD_data; end
else addwire<=AD_t; endmodule //发送模块 module
trans_t(clk_t,rst_t,en_t,BTI_t,TxD_data_t,TxD_t,recen,TxD_busy_t,addro_t,recen );
input clk_t,rst_t,en_t,BTI_t; input [7:0]TxD_data_t; output TxD_t; output TxD_busy_t; output recen;
output [7:0]addro_t;
reg TxD_t;
reg [7:0]TxD_dataReg;//寄存器 reg [7:0]addro_t;// reg [3:0]state; reg recen;
wire TxD_busy_t;
assign BaudTick = BTI_t;//波特输出
// 发送启动
wire TxD_ready = (state==0); // TxD_ready = 1 assign TxD_busy_t = ~TxD_ready; // 加载发送数据
always (posedge clk_t or negedge rst_t) if(~rst_t)
TxD_dataReg <= 8'b00000000; else if(TxD_ready && en_t) TxD_dataReg <= TxD_data_t;
// 状态机发送
always (posedge clk_t or negedge rst_t) if(~rst_t) begin
state <= 4'b0000; // 复位时发送1 TxD_t <= 1'b1;
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end else
case(state)
4'b0000: if(en_t ) begin
state <= 4'b0100; // 检测发送开始 end 4'b0100: if(BaudTick && en_t) begin
state <= 4'b1000; // 发送起始位0 TxD_t <= 1'b0; end 4'b1000: if(BaudTick && en_t) begin
state <= 4'b1001; // bit 0 if(en_t) TxD_t <= TxD_dataReg[0]; else TxD_t <= 1'b0; end 4'b1001: if(BaudTick && en_t) begin
state <= 4'b1010; // bit 1 if(en_t) TxD_t <= TxD_dataReg[1]; else TxD_t <= 1'b0; end 4'b1010: if(BaudTick && en_t) begin
state <= 4'b1011; // bit 2 if(en_t) TxD_t <= TxD_dataReg[2]; else TxD_t <= 1'b0; end 4'b1011: if(BaudTick && en_t) begin
state <= 4'b1100; // bit 3 if(en_t) TxD_t <= TxD_dataReg[3]; else TxD_t <= 1'b0; end 4'b1100: if(BaudTick && en_t) begin
state <= 4'b1101; // bit 4 if(en_t) TxD_t <= TxD_dataReg[4]; else TxD_t <= 1'b0; end 4'b1101: if(BaudTick && en_t) begin
state <= 4'b1110; // bit 5 if(en_t) TxD_t <= TxD_dataReg[5]; else TxD_t <= 1'b0; end 4'b1110: if(BaudTick && en_t) begin
state <= 4'b1111; // bit 6 if(en_t) TxD_t <= TxD_dataReg[6]; else TxD_t <= 1'b0;
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end 4'b1111: if(BaudTick && en_t) begin
state <= 4'b0010; // bit 7 if(en_t) TxD_t <= TxD_dataReg[7]; else TxD_t <= 1'b0; end 4'b0010: if(BaudTick && en_t) begin
state <= 4'b0011; // stop1 TxD_t <= 1'b1; end 4'b0011: if(BaudTick) begin
state <= 4'b0000; // stop2 TxD_t <= 1'b1; end default: if(BaudTick) begin
state <= 4'b0000; TxD_t <= 1'b1; end endcase
always (posedge clk_t or negedge rst_t) if(~rst_t)
begin recen<=0;end
else if(~TxD_ready)recen<=1; else recen<=0; //地址计数器ddress
always (posedge clk_t or negedge rst_t) if(~rst_t)
addro_t <= 8'b00000000; else if(TxD_ready && en_t) addro_t <=addro_t +1; endmodule
//波特生成模块
module BaudG(clk_b,rst_b,BTO_b,BTO_R,Wsec_b);
input clk_b,rst_b; input [2:0]Wsec_b; output BTO_b,BTO_R;
reg FT,FT8; reg [16:0]BGA; reg [16:0]BGA1;
wire BTO_b = FT; //发送波特
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