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--ADDER4B.VHD LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER4B IS PORT( C4: IN STD_LOGIC;
A4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO4: OUT STD_LOGIC); END ENTITY ADDER4B;
ARCHITECTURE ART OF ADDER4B IS
SIGNAL S5:STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL A5,B5:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
A5<='0'& A4; B5<='0'& B4; S5<=A5+B5+C4;
S4<=S5(3 DOWNTO 0); CO4<=S5(4);
END ARCHITECTURE ART;
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--ADDER8B.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ADDER8B IS PORT( C8:IN STD_LOGIC;
A8:IN STD_LOGIC_VECTOR(7 DOWNTO 0); B8:IN STD_LOGIC_VECTOR(7 DOWNTO 0); S8:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CO8:OUT STD_LOGIC); END ENTITY ADDER8B;
ARCHITECTURE ART OF ADDER8B IS COMPONENT ADDER4B IS PORT(C4:IN STD_LOGIC;
A4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B4:IN STD_LOGIC_VECTOR(3 DOWNTO 0); S4:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CO4:OUT STD_LOGIC); END COMPONENT ADDER4B; SIGNAL SC:STD_LOGIC; BEGIN
U1:ADDER4B PORT MAP(C4=>C8,A4=>A8(3 DOWNTO 0),B4=>B8(3 DOWNTO 0),S4=>S8(3 DOWNTO 0),CO4=>SC);
U2:ADDER4B PORT MAP(C4=>SC, A4=>A8(7 DOWNTO 4), B4=>B8(7 DOWNTO 4),S4=>S8 (7 DOWNTO 4),CO4=>CO8);
END ARCHITECTURE ART; ·ÂÕæÍ¼Æ¬£º