reg [3:0]led; reg k; reg [6:0]ledag1; //initial // k<=0; always @( s8) begin

if(s8==0)begin

k<=1;led<=4'b0000;ledag1<=7'b0111111;end else begin if(k==1) begin if(~s1) begin

led<=4'b1000; ledag1<=7'b0000110; k<=0; end else if(~s2) begin

led<=4'b0100;

ledag1<=7'b1011011; k<=0; end

else if(~s3) begin

led<=4'b0010; ledag1<=7'b1001111; k<=0; end else if(~s4) begin

led<=4'b0001; ledag1<=7'b1100110; k<=0; end end end end assign

ledag=ledag1; endmodule