北航verilog实验报告 下载本文

state1_spe_01=3'b100,state2_spe_01=3'b100,state3_spe_01=3'b100, state1_spe_02=3'b101,state2_spe_02=3'b101,state3_spe_02=3'b101; /*

The first always block!!!To deal with light1&switch1!!! */

always@(posedge clk10) if(!rst) begin

state1<=IDLE1; count1<=8'b0; counter1<=3'b0; end else

if(switch[0]==1'b1&&counter1<5)counter1<=counter1+1; else case(state1) IDLE1:

if(switch[0]=='b1) begin

state1<=state1_pos; count1<=79; end else begin

state1<=IDLE1; light[0]<=0; end

state1_main:

if(count1>0) begin

count1<=count1-1; end else

if(switch[0]==0) begin

state1<=state1_neg; end else

if(switch[0]==1) begin

state1<=state1_spe_01; end state1_spe_01: if(switch[0]==0) begin

state1<=state1_spe_02; count1<=39; end

else state1<=state1_spe_01;

state1_spe_02: if(count1>0) begin

count1<=count1-1; end

else

state1<=state1_neg; state1_neg: begin

light[0]<='b0; state1<=IDLE1; counter1<=3'b0; end state1_pos: begin light[0]<=1; state1<=state1_main; end

default:state1<=IDLE1; endcase /*

The second always block!!!To deal with light2&switch2!!! */

always@(posedge clk10) if(!rst) begin

state2<=IDLE2; count2<=8'b0; counter2<=3'b0; end

else

if(switch[1]==1'b1&&counter2<5)counter2<=counter2+1; else case(state2) IDLE2:

if(switch[1]=='b1) begin

state2<=state2_pos; count2<=79; end else begin

state2<=IDLE2; light[1]<='b0; end

state2_main: if(count2>0) begin

count2<=count2-1; end else

if(switch[1]==0) begin

state2<=state2_neg; end else

if(switch[1]==1) begin

state2<=state2_spe_01;