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本科生毕业设计

基于FPGA的高动态三阶锁相环设计

Based on FPGA high dynamic third-order PLL design

学 生 姓 名 专 业 学 号 指 导 教 师 学 院

李松泰

电子信息科学与技术

060412203 臧景峰 电子信息工程

2010 年 6 月

摘要

随着社会的发展，锁相环路已在通信、无线电电子学及电力系统自动化等领域中得到了极为广泛的应用。随着集成电路技术的发展，不仅能够制成频率较高的单片集成锁相环路，而且可以把整个系统集成到一个芯片上去。在基于FPGA的通信电路中，可以把全锁相环路作为一个功能模块嵌入FPGA中，构成片内锁相环。

当前，锁相环 PLL 技术在众多领域得到了广泛的应用。如信号处理 ,调制解调 ,时钟同步 ,倍频 ,频率综合等都应用到了锁相环技术。传统的锁相环由模拟电路实现 ,而全锁相环 DPLL 与传统的模拟电路实现的 PLL相比 ,具有精度高且不受温度和电压影响 ,环路带宽和中心频率编程可调 ,易于构建高阶锁相环等优点 ,并且应用在系统中时 ,不需 A/D及 D/A转换 。随着通讯技术 ,集成电路技术的飞速发展和系统芯片 SoC 的深入研究 ,锁相环 DPLL 必然会在其中得到更为广泛的应用。本文介绍了一种基于FPGA的锁相环设计 ,并对环路锁定时存在的相位抖动问题进行了重点研究 ,首次提出了使用锁定检测模块抑制锁定状态的相位抖动。介绍了当前广泛应用的锁相环的原理和基于 FPGA的设计方法。针对在锁相环应用中 ,当滤波器 K值较小时存在的相位抖动问题 ,提出了一种锁定检测模块的设计 ,通过仿真验证 ,该设计能够有效地抑制锁定状态下的相位抖动。

关键词 : FPGA 锁相环 锁定检测模块

Abstract

With the social development and phase-in communications, radio electronics and power system automation field has been very widely used. With the development of integrated circuit technology, not only made of high frequency monolithic integrated PLL, but the entire system can be integrated into a chip. FPGA-based communications circuit, all phase-locked loop can function as an embedded FPGA module, and constitutes a-chip PLL.

At present, phase-locked loop PLL technology widely in many fields of application. Such as signal processing, modulation and demodulation, clock synchronization, frequency, frequency synthesis and so applied to the PLL. Conventional PLL circuit by the analog, while all the traditional analog phase locked loop DPLL circuit of PLL compared to high accuracy and not affect the temperature and voltage, loop bandwidth and center frequency programming adjustable, easy to build advantages of high phase-locked loop, and when applied in the system, without A / D and D / A converter. With communication technology, the rapid development of integrated circuit technology and system-chip SoC in-depth study, phase-locked loop DPLL which is bound to be more widely used. This paper introduces a FPGA-based PLL design, and the existence of the phase locked loop jitter key research issues, first proposed the use of lock detection module locked phase jitter suppression. Describes the current phase-locked loop principle widely used FPGA-based design method. Applications for the PLL, when the filter is smaller K values the existence of phase jitter, a lock detection module design, through simulation, the design can effectively inhibit the locked state, the phase jitter.

Keywords: FPGA PLL lock detection module

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摘要 ........................................................................................................................................ - 0 - Abstract ................................................................................................................................. - 2 - 第一章 绪论 .......................................................................................................................... - 4 -

1.1 锁相环的研究现状 ................................................................................................. - 4 - 1.2 高动态三阶锁相环的研究意义 ............................................................................. - 4 - 第二章 锁相环相关理论概述 .............................................................................................. - 5 -

2.1模拟锁相环的基本结构及工作原理 ....................................................................... - 5 -

2.1.1模拟锁相环的基本结构 ................................................................................. - 5 - 2.1.2模拟锁相环的工作原理 ................................................................................. - 6 - 2.2三阶锁相环基本结构及工作原理 ........................................................................... - 7 -

2.2.1三阶锁相环的基本结构 ................................................................................. - 7 - 2.2.2三阶锁相环的工作原理 ................................................................................. - 8 - 2.3本次课题实现的方案 ............................................................................................... - 8 - 2.4 FPGA简要介绍 ........................................................................................................ - 9 - 第三章 三阶锁相环具体模块的实现 ................................................................................ - 11 -

3.1数字鉴相器的设计 ................................................................................................. - 11 - 3.2数字环路滤波器的设计 ......................................................................................... - 12 - 3.3数控振荡器的设计 ................................................................................................. - 14 - 3.4 N分频参数控制的设计 ......................................................................................... - 15 - 3.5 N分频器的设计 ..................................................................................................... - 16 - 3.6数模DAC转换模块的设计 .................................................................................. - 17 - 3.7三阶锁相环的顶层模块 ......................................................................................... - 18 - 第四章 三阶锁相环仿真 .................................................................................................... - 18 -

4.1 三阶锁相环的功能仿真 ........................................................................................ - 19 - 4.2 三阶锁相环的时序仿真 ........................................................................................ - 19 - 4.3 三阶锁相环仿真的实测 ......................................................................................... - 20 - 结论 ...................................................................................................................................... - 24 - 致谢 ...................................................................................................................................... - 25 - 参考文献 .............................................................................................................................. - 26 - 附 录 .................................................................................................................................. - 27 -

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