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end process; end;

6顶层文件； library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity DigitalClock is

port(clk,en,rst : in std_logic; ADJEN : in std_logic;

AlarmEn : in std_logic; alarmADJ : in std_logic;

ADJ : in std_logic_vector(3 downto 0); sound : out std_logic;

hour_unit : out std_logic_vector(3 downto 0); hour_decade : out std_logic_vector(3 downto 0); min_unit : out std_logic_vector(3 downto 0); min_decade : out std_logic_vector(3 downto 0); sec_unit : out std_logic_vector(3 downto 0); sec_decade : out std_logic_vector(3 downto 0); dote1 : out std_logic_vector(3 downto 0); dote2 : out std_logic_vector(3 downto 0)); end ;

architecture bhv of DigitalClock is component hour

port(rst,carry,en : in std_logic; ADJclk,ADJEN : in std_logic;

ADJ : in std_logic_vector(3 downto 0); decade,unit : out std_logic_vector(3 downto 0)); end component; component min

port(rst,carry,en : in std_logic; ADJclk,ADJEN : in std_logic;

ADJ : in std_logic_vector(3 downto 0); carryout : out std_logic;

decade,unit : out std_logic_vector(3 downto 0)); end component; component sec

port(rst,clk,en : in std_logic; ADJEN : in std_logic;

carryout : out std_logic;

decade,unit : out std_logic_vector(3 downto 0)); end component;

component alarm

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port(clk,en,ADJclk : in std_logic; alarmADJ : in std_logic; AlarmEn : in std_logic;

ADJ : in std_logic_vector(3 downto 0); hour_unit : in std_logic_vector(3 downto 0); hour_decade : in std_logic_vector(3 downto 0); min_unit : in std_logic_vector(3 downto 0); min_decade : in std_logic_vector(3 downto 0); ADJhour_unit : out std_logic_vector(3 downto 0); ADJhour_decade : out std_logic_vector(3 downto 0); ADJmin_unit : out std_logic_vector(3 downto 0); ADJmin_decade : out std_logic_vector(3 downto 0); sound : out std_logic); end component;

component PrescalClk

port(clkin : in std_logic;

clkout_1Hz : out std_logic; clkout_4Hz : out std_logic); end component;

signal carry1,carry2,clk_1Hz,clk_4Hz : std_logic;

signal hour1,hour2,min1,min2 ,ADJhour1,ADJhour2,ADJmin1,ADJmin2 : std_logic_vector(3 downto 0); begin U1 : hour port map(rst=>rst,ADJclk=>clk_4Hz,en=>en,carry=>carry1,ADJEN=>ADJEN,ADJ=>ADJ,decade=>hour1,unit=>hour2); U2 : min port map(rst=>rst,ADJclk=>clk_4Hz,en=>en,carry=>carry2,carryout=>carry1,ADJEN=>ADJEN,ADJ=>ADJ,decade=>min1,unit=>min2); U3 : sec port map(rst=>rst,clk=>clk_1Hz,en=>en,carryout=>carry2,decade=>sec_decade,unit=>sec_unit,ADJEN=>ADJEN); U4 : alarm port map(clk=>clk_1Hz,en=>en,ADJclk=>clk_4Hz,alarmADJ=>alarmADJ,AlarmEn=>AlarmEn,ADJ=>ADJ,

hour_unit=>hour2,hour_decade=>hour1,min_unit=>min2,min_decade=>min1,

ADJhour_decade=>ADJhour1,ADJhour_unit=>ADJhour2,ADJmin_decade=>ADJmin1,ADJmin_unit=>ADJmin2 ,sound=>sound); U5 : PrescalClk port map(clkin=>clk,clkout_1Hz=>clk_1Hz,clkout_4Hz=>clk_4Hz);

process(hour1,hour2,min1,min2,alarmADJ,ADJhour1,ADJhour2,ADJmin1,

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ADJmin2) begin

if(alarmADJ='0') then hour_decade<=hour1; hour_unit<=hour2; min_decade<=min1; min_unit<=min2; else

hour_decade<=ADJhour1; hour_unit<=ADJhour2; min_decade<=ADJmin1; min_unit<=ADJmin2; end if;

dote1<=\ dote2<=\ end process; end;

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