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文章发布时间 : 2026/6/16 16:32:56星期二

电梯控制器

一、实验题目

以交大一附院住院大楼为例设计一款电梯控制器，能够适用于该大楼所有电梯。（交大一附院住院大楼地下2层，地上20层，共有8部电梯，1号梯停奇数层，2~4号梯停10层以下，5~7号梯停10层以上，8号梯停偶数层。）

二、实验目的

1）掌握verilog语言对组合逻辑的描述；

2）学习testbench的设计方法

3）掌握仿真器（modelsim/verilog/VCS）的仿真、调试、波形输出等常用技巧；

4）掌握DC约束规划方法、综合器使用、结果查看、后仿真等； 5）熟悉简单芯片从规划到实现方法。

三、实验内容

3.1电梯内部以及外部按钮的输出。

1098720191817161514131211Request[21:0]Call_up65432Call_down1B1B2 图1 电梯按钮

3.2设计一个电梯类型控制器模块，使其控制电梯既能奇数层停，也能偶数

层停，也能10层之上，也能10层之下。这里主要使用了组合逻辑电路，通过组合电路来控制输出信号。

RESETRequest_inCall_up_inCall_down_inEVENODDRequest_outCall_up_outCall_down_outDOWN10UP10

图2电梯类型开关

3.3分频器模块，这里主控模块使用了1HZ的时钟信号，所以，我们需要使用分频器来产生一个1HZ的时钟信号，1HZ的时钟信号主要用来控制电梯状态的转化，包括上升一层，下降一层，暂停，开门，关门，待命。

3.4主控模块，这里是电梯控制的核心模块，主要实现的电梯上下楼层的判断。

WAIT UP DOWN UPSTOP DOWNSTOP OPENDOOR CLOSEDOOR 图3 电梯状态转化

3.5显示模块，显示出电梯在运动过程中当前所在的楼层，使用了动态扫描。

[1:0][6:0] 图4 数码管动态显示

3.6电梯控制器的流程图

初始化停止等待否是否有请求是目标层与本层是否同层否判断电梯运行方向否电梯运行楼层检测图6电梯控制器流程图

是是否停止运行关门是开门电梯停止是是否目标层否四、实验结果

实验中，为了方便仿真查看，所产生的时钟信号并不是1s和10ns，特此声明

4．1 QUARTUSII综合结果

图5 总的综合电路

4．2Modelsim前仿真结果

4.2.1

此时，电梯外部有19层和20层的向下请求，13层的向上请求，以及电梯内部的5层的请求，由于电梯类型为ODD，所以20层的向下请求被屏蔽。根据设计规则，电梯会运行到5层后，开门5S，然后关门，并且动态输出电梯层数05。

图6仿真1

4.2.2

电梯停在五层，外部有19层和118层的向下请求，8层的向上请求，电梯内部我请求，因为此时电梯类型为UP10所以8层的想上请求被屏蔽，同时电梯停在五层之前的动作是向上的，所以，电梯先响应19层的向下请求。到达19层后，电梯开门5S，然后关门。运动过程中，数码管动态显示楼层

图7 仿真2

4.2.3

电梯停在19层，此时，外部有20层、12层、4层的向下请求，14层和8层的向上请求，以及电梯内部6层和15的请求。因为此时的电梯类型为BLOW10所以，20层、12层向下请求，14层向上请求，电梯内部15层请求被屏蔽，同时电梯停在19层之前的动作是向下的，所以，电梯先响应内部6层的请求。到达6层后，电梯开门5s，然后关门。运动过程中，数码管动态显示楼层

图8 仿真3

4.2.3

电梯停在6层，此时只有2层和一层的向下请求，所以响应2层的向下请求，到达2层后，开门5S，然后关门。然后有1层的电梯内部请求，电梯回到1层后，电梯内外均没有1任何按键请求，电梯处于WAIT状态，电梯门处于关闭态。

图9 仿真4

4．3覆盖率报告

图10覆盖率报告

图11 toggle报告

4．4 DC综合结果

图12顶层模块

图13 模块之间具体连接

图14 分频器模块

图15 电梯类型控制模块

图16数码管显示模块

图17 DC命令运行脚本tcl

图18 DC生成的面积报告

综合后生成的约束报告（只报告违例）

19 DC

图图20 DC综合后生成的时序报告

五、实验结论

本次EDA实验使我对整个设计流程有了基本的认识，从代码设计，功能设计，以及后面的功能仿真，代码覆盖率查看，和DC综合约束，生成时序报告的查看，错误的修改，以及最后的后仿真部分，查看最长数据延时，都有了基本的了解。对一些TCL命令也有了初步的认知。

但是，此次设计中不足之处很多，首先是功能方面，没有实现对电梯运动的电机控制，没有加入对电梯门控的信号，自身设计水平还有待提高，代码风格很差，任重而道远。

在DC综合这块，存在很大的问题，很多约束不会添加，违例报告不会修改，还是需要长期的学习才能掌握！

附录

代码1电梯类型控制 module

floorstyle(clk,reset,floor_full,floor_odd,floor_even,floor_blow10,floor_up10,request_all,

call_up_all,call_down_all,call_up_out,request_all_out,call_down_out); input clk,reset,floor_full,floor_odd,floor_even,floor_blow10,floor_up10; input [21:0]request_all;

input [20:0]call_up_all,call_down_all; output reg [21:0]request_all_out;

output reg [20:0]call_up_out,call_down_out; always @(posedgeclk ) begin

if(reset==1'b1) begin

request_all_out=22'b0000000000000000000000 &request_all; call_up_out=22'b000000000000000000000 &call_up_all;

call_down_out=22'b000000000000000000000 &call_down_all; end else begin

if(floor_odd==1'b1) begin

request_all_out=22'b0101010101010101010111 &request_all; call_up_out=21'b101010101010101010111 &call_up_all;

call_down_out=21'b010101010101010101011 &call_down_all; end

else if(floor_even==1'b1) begin

request_all_out=22'b1010101010101010101011 &request_all; call_up_out=21'b010101010101010101011 &call_up_all;

call_down_out=21'b101010101010101010101 &call_down_all; end

else if(floor_blow10==1'b1) begin

request_all_out=22'b0000000000111111111111 &request_all; call_up_out=21'b000000000111111111111 &call_up_all;

call_down_out=21'b000000000011111111111 &call_down_all; end

else if(floor_up10==1'b1) begin

request_all_out=22'b1111111111000000000011 &request_all; call_up_out=21'b111111111000000000011 &call_up_all;

call_down_out=21'b111111111100000000001 &call_down_all; end

else if(floor_full==1'b1) begin

request_all_out=22'b1111111111111111111111 &request_all; call_up_out=21'b111111111111111111111 &call_up_all;

call_down_out=21'b111111111111111111111 &call_down_all; end end end

endmodule

代码2 分频器模块

module frequeny_1ns(cp_50M,reset,cp_1); input cp_50M,reset; output cp_1;

reg [27:0] counter_1; reg cp_1;

always@(posedge cp_50M ) begin if(reset) begin

counter_1<=28'h0000000; cp_1<=0; end

else if(counter_1==28'd1000)//counter_1==28'h17D7840 1ns begin

cp_1<=~cp_1;

counter_1<=28'h0000000; end else

counter_1<=counter_1+1'b1; end

endmodule

代码3主控模块 module

control(clk,reset,call_up_b2,call_up_b1,call_up_1,call_up_2,call_up_3,call_up_4,

call_up_5,call_up_6,call_up_7,call_up_8,call_up_9,call_up_10,call_up_11,call_up_12,

call_up_13,call_up_14,call_up_15,call_up_16,call_up_17,call_up_18,call_up_19,

call_down_b1,call_down_1,call_down_2,call_down_3,call_down_4,call_down_5,call_down_6,

call_down_7,call_down_8,call_down_9,call_down_10,call_down_11,call_down_12,call_down_13,

call_down_14,call_down_15,call_down_16,call_down_17,call_down_18,call_down_19,call_down_20,

request_b2,request_b1,request_1,request_2,request_3,request_4,request_5,request_6,request_7,

request_8,request_9,request_10,request_11,request_12,request_13,request_14,request_15,

request_16,request_17,request_18,request_19,request_20,PosOut,LiftState); output [21:0]PosOut; output [6:0] LiftState;

input clk,reset,call_up_b2,call_up_b1,call_up_1,call_up_2,call_up_3,call_up_4,

call_up_5,call_up_6,call_up_7,call_up_8,call_up_9,call_up_10,call_up_11,call_up_12,

call_up_13,call_up_14,call_up_15,call_up_16,call_up_17,call_up_18,call_up_19,

call_down_b1,call_down_1,call_down_2,call_down_3,call_down_4,call_down_5,call_down_6,

call_down_7,call_down_8,call_down_9,call_down_10,call_down_11,call_down_12,call_down_13,

call_down_14,call_down_15,call_down_16,call_down_17,call_down_18,call_down_19,call_down_20,

request_b2,request_b1,request_1,request_2,request_3,request_4,request_5,request

_6,request_7,

request_8,request_9,request_10,request_11,request_12,request_13,request_14,request_15,

request_16,request_17,request_18,request_19,request_20; reg [21:0]pos,PosOut; reg [2:0] count; regDoorFlag;

reg [1:0] UpDnFlag;

reg [6:0] LiftState,NextState;

reg [21:0] up_all,down_all,request_all; parameter WAIT=7'b0000001, UP=7'b0000010, DOWN=7'b0000100, UPSTOP=7'b0001000,

DOWNSTOP=7'b0010000, OPENDOOR=7'b0100000, CLOSEDOOR=7'b1000000; parameter

FLOORB2=22'b0000000000000000000001,FLOORB1=22'b0000000000000000000010,

FLOOR1=22'b0000000000000000000100, FLOOR2=22'b0000000000000000001000,

FLOOR3=22'b0000000000000000010000, FLOOR4=22'b0000000000000000100000,

FLOOR5=22'b0000000000000001000000, FLOOR6=22'b0000000000000010000000,

FLOOR7=22'b0000000000000100000000, FLOOR8=22'b0000000000001000000000,

FLOOR9=22'b0000000000010000000000, FLOOR10=22'b0000000000100000000000,

FLOOR11=22'b0000000001000000000000,FLOOR12=22'b0000000010000000000000,

FLOOR13=22'b0000000100000000000000,FLOOR14=22'b0000001000000000000000,

FLOOR15=22'b0000010000000000000000,FLOOR16=22'b0000100000000000000000,

FLOOR17=22'b0001000000000000000000,FLOOR18=22'b0010000000000000000000,

FLOOR19=22'b0100000000000000000000,FLOOR20=22'b1000000000000000000000;

parameter TRUE=1'b1, FALSE=1'b0;

parameter OPEN=1'b1, CLOSED=1'b0;

parameter UPFLAG=2'b01,DNFLAG=2'b10,STATIC=2'b00; always

@(call_up_b2,call_up_b1,call_up_1,call_up_2,call_up_3,call_up_4,call_up_5,

call_up_6,call_up_7,call_up_8,call_up_9,call_up_10,call_up_11,call_up_12,

call_up_13,call_up_14,call_up_15,call_up_16,call_up_17,call_up_18,call_up_19)

up_all={1'b0,call_up_19,call_up_18,call_up_17,call_up_16,call_up_15,call_up_14,

call_up_13,call_up_12,call_up_11,call_up_10,call_up_9,call_up_8,call_up_7,

call_up_6,call_up_5,call_up_4,call_up_3,call_up_2,call_up_1,call_up_b1, call_up_b2}; always

@(call_down_b1,call_down_1,call_down_2,call_down_3,call_down_4,call_down_5,call_down_6,

call_down_7,call_down_8,call_down_9,call_down_10,call_down_11,call_down_12,call_down_13,

call_down_14,call_down_15,call_down_16,call_down_17,call_down_18,call_down_19,call_down_20)

down_all={call_down_20,call_down_19,call_down_18,call_down_17,call_down_16,call_down_15,

call_down_14,call_down_13,call_down_12,call_down_11,call_down_10,call_down_9,

call_down_8,call_down_7,call_down_6,call_down_5,call_down_4,call_down_3, call_down_2,call_down_1,call_down_b1,1'b0}; always

@(request_b2,request_b1,request_1,request_2,request_3,request_4,request_5,request_6,request_7,

request_8,request_9,request_10,request_11,request_12,request_13,request_14,request_15,

request_16,request_17,request_18,request_19,request_20)

request_all={request_20,request_19,request_18,request_17,request_16,request_15, request_14,request_13,request_12,request_11,request_10,request_9,

request_8,request_7,request_6,request_5,request_4,request_3,

request_2,request_1,request_b1,request_b2}; always @(posedgeclk ) if(reset)

count<=0;

else if((NextState==OPENDOOR)&&(count<5)) count<=count+1; else

count<=0; always @(posedgeclk ) if(reset) begin LiftState<=WAIT; end else

LiftState<=NextState;

always @(LiftState or up_all or down_all or request_all or pos or count or UpDnFlag)

case(LiftState) WAIT: begin if(request_all>0)

begin

if((request_all&pos)>0) NextState=OPENDOOR;

else if(request_all>pos) NextState=UP;

else NextState=DOWN; end

else if((up_all&pos)||(down_all&pos)) begin NextState=OPENDOOR;

end

else if((up_all>pos)||(down_all>pos)) NextState=UP;

else if(up_all||down_all) NextState=DOWN;

else NextState=WAIT;

end UP:

begin

if((request_all&pos)||(up_all&pos)) NextState=UPSTOP;

else if((request_all>pos)||(up_all>pos)) NextState=UP;

else if(down_all>0) begin

if((down_all>pos)&&((down_all^pos)>pos)) NextState=UP;

else if((down_all&pos)||(pos

else if((down_all&pos)&&(pos==FLOOR20)) NextState=DOWNSTOP;

else NextState=DOWN;

end

else if(request_all||up_all) NextState=DOWN;

else NextState=WAIT;

end DOWN: begin if((request_all&pos)||(down_all&pos)) NextState=DOWNSTOP; else

//request_all

if(((request_all&FLOORB2)

((request_all&FLOOR17)

//down_all

if(((down_all&FLOORB2)

else if (up_all>0) begin

//up_all

if(((up_all&FLOORB2)

((up_all&FLOOR10)

else if((up_all&pos)&&(pos>FLOORB2)) NextState=DOWNSTOP;

else if((up_all&pos)&&(pos==FLOORB2)) NextState=UPSTOP; else NextState=UP;

end

else if(request_all||down_all) NextState=UP;

else NextState=WAIT;

end UPSTOP: begin NextState=OPENDOOR; end DOWNSTOP: begin NextState=OPENDOOR; end OPENDOOR: begin

if(count<5) NextState=OPENDOOR;

else NextState=CLOSEDOOR; end CLOSEDOOR: begin

if(UpDnFlag==UPFLAG) begin if((request_all&pos)||(up_all&pos))

NextState=OPENDOOR;

else if((request_all>pos)||(up_all>pos)) NextState=UP;

else if(down_all>0)//?????? begin

if((down_all>pos)&&((down_all^pos)>pos)) NextState=UP;

else if((down_all&pos)>0) NextState=OPENDOOR;

else NextState=DOWN;

end

else if(request_all||up_all) NextState=DOWN;

else NextState=WAIT;

end

else if(UpDnFlag==DNFLAG) begin

if((request_all&pos)||(down_all&pos)) NextState=OPENDOOR;

else

if(((request_all&FLOORB2)

NextState=DOWN;

else //down_all

if(((down_all&FLOORB2)

else if (up_all>0) begin

//up_all

if(((up_all&FLOORB2)

((up_all&FLOOR14)

else if((up_all&pos)>0) NextState=OPENDOOR;

NextState=UP;//

NextState=UP;

NextState=WAIT;//

NextState=OPENDOOR;

NextState=UP;

NextState=DOWN;

NextState=OPENDOOR;

NextState=UP;

NextState=DOWN; NextState=WAIT;

else end

else if(request_all||down_all) else end else begin

if(request_all>0) begin

if((request_all&pos)>0) else if(request_all>pos) else end

else if((up_all&pos)||(down_all&pos)) begin end

else if((up_all>pos)||(down_all>pos)) else if(up_all||down_all) else

begin end end end default: NextState=WAIT;

endcase

always @(posedgeclk )//output if(reset) begin pos<=FLOOR1;

DoorFlag<=CLOSED; UpDnFlag<=STATIC; end

else begin PosOut<=pos;

case(NextState) WAIT: begin pos<=pos;

DoorFlag<=CLOSED; UpDnFlag<=STATIC;

end UP:

begin pos<=pos<<1;

DoorFlag<=CLOSED; UpDnFlag<=UPFLAG;

end DOWN: begin pos<=pos>>1;

DoorFlag<=CLOSED; UpDnFlag<=DNFLAG;

end UPSTOP: begin pos<=pos;

DoorFlag<=CLOSED; UpDnFlag<=UPFLAG;

end DOWNSTOP: begin pos<=pos;

DoorFlag<=CLOSED; UpDnFlag<=DNFLAG;

end

OPENDOOR: begin pos<=pos;

DoorFlag<=OPEN; UpDnFlag<=UpDnFlag; end

CLOSEDOOR: begin pos<=pos;

DoorFlag<=CLOSED; UpDnFlag<=UpDnFlag;

end default: begin pos<=FLOOR1; DoorFlag<=CLOSED; UpDnFlag<=STATIC; end endcase

end endmodule

代码4数码管显示模块包括两部分，动态扫描和解码。

module display_num(clk,reset,PosOut,row_scan_sig,colume_scan_sig); input clk,reset; input [21:0]PosOut;

output [6:0]row_scan_sig; output [1:0]colume_scan_sig; wire [6:0]ten_smg_data; wire [6:0]one_smg_data;

num u1(.clk(clk),.reset(reset),.PosOut(PosOut),

.ten_smg_data(ten_smg_data),.one_smg_data(one_smg_data)); scan u2(.clk(clk),.reset(reset),.ten_smg_data(ten_smg_data),

.one_smg_data(one_smg_data),.row_scan_sig(row_scan_sig), .colume_scan_sig(colume_scan_sig)); Endmodule 动态扫描

module scan(clk,reset,ten_smg_data,one_smg_data,row_scan_sig,colume_scan_sig); input clk,reset;

input [6:0]ten_smg_data,one_smg_data; output reg [6:0]row_scan_sig; output reg [1:0]colume_scan_sig;

parameter T10MS = 19'd1999;//T10MS = 19'd499_999; reg [18:0]count1;

always @(posedgeclk ) if(reset)

count1<=19'b0;

else if(count1==T10MS) count1<=19'b0; else

count1<=count1+19'b1; reg [1:0]t1;

always @(posedgeclk ) if(reset==1'b1) t1<=2'd0;

else if(t1==2'd2) t1<=2'd0;

else if(count1==T10MS) t1<=t1+1'b1;

always @(posedgeclk) if(reset==1'b1) row_scan_sig<=2'd0;

else if(count1==T10MS) case(t1)

2'd0:row_scan_sig<=ten_smg_data; 2'b1:row_scan_sig<=one_smg_data; endcase

reg [18:0]count2;

always @(posedgeclk ) if(reset)

count2<=19'b0;

else if(count2==T10MS) count2<=19'b0; else

count2<=count2+19'b1; reg [1:0]t2;

always @(posedgeclk) if(reset==1'b1) t2<=2'd0;

else if(t2==2'd2) t2<=2'd0;

else if(count1==T10MS) t2<=t2+1'b1;

always @(posedgeclk) if(reset==1'b1)

colume_scan_sig<=2'd0;

else if(count1==T10MS) case(t2)

2'd0:colume_scan_sig<=2'b10; 2'b1:colume_scan_sig<=2'b01; endcase endmodule 解码

module num(reset,clk,PosOut,ten_smg_data,one_smg_data); input clk,reset; input [21:0]PosOut;

output reg [6:0]ten_smg_data,one_smg_data;

parameter _0 = 7'b100_0000, _1 = 7'b111_1001, _2 = 7'b010_0100, _3 = 7'b011_0000, _4 = 7'b001_1001, _5 = 7'b001_0010, _6 = 7'b000_0010, _7 = 7'b111_1000, _8 = 7'b000_0000, _9 = 7'b001_0000, _C = 7'b100_0110; reg [3:0]ten_data,one_data; reg [4:0]num;

always @(posedgeclk ) begin

case(PosOut)

22'b0000000000000000000001: num<=5'd1; 22'b0000000000000000000010: num<=5'd2; 22'b0000000000000000000100: num<=5'd3; 22'b0000000000000000001000: num<=5'd4; 22'b0000000000000000010000: num<=5'd5; 22'b0000000000000000100000: num<=5'd6; 22'b0000000000000001000000: num<=5'd7; 22'b0000000000000010000000: num<=5'd8; 22'b0000000000000100000000: num<=5'd9; 22'b0000000000001000000000: num<=5'd10; 22'b0000000000010000000000: num<=5'd11; 22'b0000000000100000000000: num<=5'd12; 22'b0000000001000000000000: num<=5'd13; 22'b0000000010000000000000: num<=5'd14; 22'b0000000100000000000000: num<=5'd15; 22'b0000001000000000000000: num<=5'd16; 22'b0000010000000000000000: num<=5'd17; 22'b0000100000000000000000: num<=5'd18; 22'b0001000000000000000000: num<=5'd19; 22'b0010000000000000000000: num<=5'd20; 22'b0100000000000000000000: num<=5'd21; 22'b1000000000000000000000: num<=5'd22; endcase end

always @(posedgeclk ) if(reset) begin

ten_data<=4'b0; one_data<=4'b0; end

else if(num>=5'd3) begin

ten_data<=(num-5'd2)/10; one_data<=(num-5'd2); end

else if(num==5'd1) begin

ten_data<=4'd11; one_data<=4'd2; end

else if(num==5'd2) begin

ten_data<=4'd11; one_data<=4'd1; end

always @(posedgeclk ) if(reset)

ten_smg_data<=7'b1111111; else

case(ten_data)

4'd0:ten_smg_data<=_0; 4'd1:ten_smg_data<=_1; 4'd2:ten_smg_data<=_2; 4'd3:ten_smg_data<=_3; 4'd4:ten_smg_data<=_4; 4'd5:ten_smg_data<=_5; 4'd6:ten_smg_data<=_6; 4'd7:ten_smg_data<=_7; 4'd8:ten_smg_data<=_8; 4'd9:ten_smg_data<=_9; 4'd11:ten_smg_data<=_C; endcase

always @(posedgeclk ) if(reset==1'b1)

one_smg_data<=7'b1111111; else

case(one_data)

4'd0:one_smg_data<=_0;

4'd1:one_smg_data<=_1; 4'd2:one_smg_data<=_2; 4'd3:one_smg_data<=_3; 4'd4:one_smg_data<=_4; 4'd5:one_smg_data<=_5; 4'd6:one_smg_data<=_6; 4'd7:one_smg_data<=_7; 4'd8:one_smg_data<=_8; 4'd9:one_smg_data<=_9; endcase endmodule

代码5顶层模块 module

main(clk,rst1,rst2,floor_full,floor_odd,floor_even,floor_blow10,floor_up10,request_all,

call_up_all,call_down_all,row_scan_sig,colume_scan_sig,LiftState); input clk,floor_full,floor_odd,floor_even,floor_blow10,floor_up10; input rst1,rst2;

input [21:0]request_all;

input [20:0]call_up_all,call_down_all; output [6:0]row_scan_sig; output [1:0]colume_scan_sig; output [6:0] LiftState;

wire [21:0]request_all_out;

wire [20:0]call_up_out,call_down_out; wire clk_1s;

wire [21:0]PosOut;

frequeny_1ns u1(.cp_50M(clk),.reset(rst1),.cp_1(clk_1s));

floorstyle u2(.clk(clk),.reset(rst1),.floor_full(floor_full),.floor_odd(floor_odd),

.floor_even(floor_even),.floor_blow10(floor_blow10),.floor_up10(floor_up10),

.request_all(request_all),.call_up_all(call_up_all),.call_down_all(call_down_all),

.call_up_out(call_up_out),.request_all_out(request_all_out), .call_down_out(call_down_out)); control

u3(.clk(clk_1s),.reset(rst2),.call_up_b2(call_up_out[0]),.call_up_b1(call_up_out[1]), .call_up_1(call_up_out[2]),.call_up_2(call_up_out[3]),.call_up_3(call_up_out[4]),

.call_up_4(call_up_out[5]),.call_up_5(call_up_out[6]),.call_up_6(call_up_out[7]),

.call_up_7(call_up_out[8]),.call_up_8(call_up_out[9]),.call_up_9(call_up_out[10]),

.call_up_10(call_up_out[11]),.call_up_11(call_up_out[12]),.call_up_12(

call_up_out[13]),

.call_up_13(call_up_out[14]),.call_up_14(call_up_out[15]),.call_up_15(call_up_out[16]),

.call_up_16(call_up_out[17]),.call_up_17(call_up_out[18]),.call_up_18(call_up_out[19]),

.call_up_19(call_up_out[20]),

.call_down_b1(call_down_out[0]),.call_down_1(call_down_out[1]),.call_down_2(call_down_out[2]),

.call_down_3(call_down_out[3]),.call_down_4(call_down_out[4]),.call_down_5(call_down_out[5]),

.call_down_6(call_down_out[6]),.call_down_7(call_down_out[7]),.call_down_8(call_down_out[8]),

.call_down_9(call_down_out[9]),.call_down_10(call_down_out[10]),.call_down_11(call_down_out[11]),

.call_down_12(call_down_out[12]),.call_down_13(call_down_out[13]),.call_down_14(call_down_out[14]),

.call_down_15(call_down_out[15]),.call_down_16(call_down_out[16]),.call_down_17(call_down_out[17]),

.call_down_18(call_down_out[18]),.call_down_19(call_down_out[19]),.call_down_20(call_down_out[20]),

.request_b2(request_all_out[0]),.request_b1(request_all_out[1]),.request_1(request_all_out[2]),

.request_2(request_all_out[3]),.request_3(request_all_out[4]),.request_4(request_all_out[5]),

.request_5(request_all_out[6]),.request_6(request_all_out[7]),.request_7(request_all_out[8]),

.request_8(request_all_out[9]),.request_9(request_all_out[10]),.request_10(request_all_out[11]),

.request_11(request_all_out[12]),.request_12(request_all_out[13]),.request_13(request_all_out[14]),

.request_14(request_all_out[15]),.request_15(request_all_out[16]),.request_16(request_all_out[17]),

.request_17(request_all_out[18]),.request_18(request_all_out[19]),.request_19(request_all_out[20]),

.request_20(request_all_out[21]),.PosOut(PosOut),.LiftState(LiftState)); display_num

u4(.clk(clk),.reset(rst1),.PosOut(PosOut),.row_scan_sig(row_scan_sig),.colume_scan_sig(colume_scan_sig)); endmodule

代码6 测试模块 `timescale 1ns/1ns module main_tb;

reg clk,floor_full,floor_odd,floor_even,floor_blow10,floor_up10; reg rst1,rst2;

reg [21:0]request_all;

reg [20:0]call_up_all,call_down_all; wire [6:0]row_scan_sig; wire [1:0]colume_scan_sig; wire [6:0] LiftState;

main u1(.clk(clk),.rst1(rst1),.rst2(rst2),.floor_full(floor_full), .floor_odd(floor_odd),.floor_even(floor_even), .floor_blow10(floor_blow10),

.floor_up10(floor_up10),.request_all(request_all), .call_up_all(call_up_all),.call_down_all(call_down_all),

.row_scan_sig(row_scan_sig),.colume_scan_sig(colume_scan_sig), .LiftState(LiftState)); always #5 clk =~clk; initial begin clk=0;

rst1=1; rst2=1; floor_odd=1; floor_even=0;

floor_blow10=0; floor_up10=0; floor_full=0;

request_all=22'd0; call_up_all=21'd0;

call_down_all=21'b110000000000000000000;//floor19 floor20 call_up_all= 21'b000000100000000000000;//floor13 request_all=22'b00_0000_0000_0000_0100_0000;//floor5 end initial begin

#10 rst1=0;

@(posedge u1.clk_1s) #10 rst2=0;

wait(u1.PosOut==22'b00_0000_0000_0000_0100_0000)//floor5 begin

floor_odd=0;

floor_up10=1;

call_down_all=21'b011000000000000000000;//floor19 call_up_all= 21'b000000000001000000000;//floor8 request_all=22'd0; end

wait(u1.PosOut==22'b01_0000_0000_0000_0000_0000)//floor19 begin

floor_up10=0; floor_blow10=1;

call_down_all=21'b100000001000000010000;//floor20 floor12 floor4 call_up_all= 21'b000001000001000000000;//floor8 floor14

request_all=22'b00_0001_0000_0000_1000_0000;//floor6 floor15 end

wait(u1.PosOut==22'b00_0000_0000_0000_1000_0000)//floor6 begin

floor_blow10=0; floor_even=1;

call_down_all=21'b000000000000000000110;//floor2 floor1 call_up_all= 21'b000000000000000000000; request_all=22'd0; end

wait(u1.PosOut==22'b00_0000_0000_0000_0000_1000)//floor2 begin

floor_even=0; floor_full=1;

call_down_all=21'd0; call_up_all=21'd0;

request_all=22'b00_0000_0000_0000_0000_0100;//floor1 end

wait(u1.PosOut==22'b00_0000_0000_0000_0000_0100)//foor1 request_all=22'd0;

wait(LiftState==7'b0000001)

@(posedge u1.clk_1s) #500 $stop; end

endmodule

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