STM32F10x - TIM - ͼÎÄ ÏÂÔØ±¾ÎÄ

º¯ÊýÔ­ÐÎ void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) ¹¦ÄÜÃèÊö ÔÚÒ»¸öÍⲿʼþ(ETRF¸ßµçƽ)ʱÇå³ý»ò±£³ÖOCREF1ÐźŠÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλ״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλµÄÖµÁоÙÈçÏÂ±í¡£ Table 520. TIM_OCClearÖµ TIM_OCClear ÃèÊö/CCMR1.bit7 #defineÖµ TIM_OCClear_Enable TIMxÊä³ö±È½ÏÇå³ýʹÄÜ 0x0080 TIM_OCClear_Disable TIMxÊä³ö±È½ÏÇå³ýʧÄÜ 0x0000 Àý£º

/* Enable the TIM2 Channel1 Ouput Compare Refence clear bit */ TIM_ClearOC1Ref(TIM2, TIM_OCClear_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) {

u16 tmpccmr1 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));

tmpccmr1 = TIMx->CCMR1;

/* Reset the OC1CE Bit */

tmpccmr1 &= CCMR_OC13CE_Reset;//0xFF7F,CCMR1.bit7//=1£¨Ò»µ©¼ì²âµ½ETRFÊäÈë¸ßµçƽ£¬Çå³ýOCxREF=0£©

/* Enable or Disable the Output Compare Clear Bit */ tmpccmr1 |= TIM_OCClear;

/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }

19.2.36 º¯ÊýTIM_ClearOC2Ref

Table 521. º¯Êý TIM_ClearOC2Ref º¯ÊýÃû TIM_ClearOC2Ref º¯ÊýÔ­ÐÎ void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) ¹¦ÄÜÃèÊö ÔÚÒ»¸öÍⲿʼþ(ETRF¸ßµçƽ)ʱÇå³ý»ò±£³ÖOCREF2ÐźŠÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλ״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλµÄÖµÁоÙÈçÏÂ±í¡£ ¡¾TIM_ClearOC1Ref¡¿ TIM_OCClear ÃèÊö/CCMR1.bit7 #defineÖµ TIM_OCClear_Enable TIMxÊä³ö±È½ÏÇå³ýʹÄÜ 0x0080 TIM_OCClear_Disable TIMxÊä³ö±È½ÏÇå³ýʧÄÜ 0x0000 Àý£º /* Enable the TIM2 Channel2 Ouput Compare Refence clear bit */ TIM_ClearOC2Ref(TIM2, TIM_OCClear_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) {

u16 tmpccmr1 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));

tmpccmr1 = TIMx->CCMR1;

/* Reset the OC2CE Bit */

tmpccmr1 &= CCMR_OC24CE_Reset;//0x7FFF,CCMR1.bit15//=1£¨Ò»µ©¼ì²âµ½ETRFÊäÈë¸ßµçƽ£¬Çå³ýOCxREF=0£©

/* Enable or Disable the Output Compare Clear Bit */

tmpccmr1 |= (u16)(TIM_OCClear << 8);// CCMR1.OC2CE±ÈCCMR1.OC1CE¸ß8λ

/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }

19.2.37 º¯ÊýTIM_ClearOC3Ref

Table 522. º¯ÊýTIM_ClearOC3Ref º¯ÊýÃû TIM_ClearOC3Ref º¯ÊýÔ­ÐÎ void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) ¹¦ÄÜÃèÊö ÔÚÒ»¸öÍⲿʼþ(ETRF¸ßµçƽ)ʱÇå³ý»òÕß±£³ÖOCREF3ÐźŠÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλ״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλµÄÖµÁоÙÈçÏÂ±í¡£ ¡¾TIM_ClearOC1Ref¡¿ TIM_OCClear ÃèÊö/CCMR1.bit7 #defineÖµ TIM_OCClear_Enable TIMxÊä³ö±È½ÏÇå³ýʹÄÜ 0x0080 TIM_OCClear_Disable TIMxÊä³ö±È½ÏÇå³ýʧÄÜ 0x0000 Àý£º /* Enable the TIM2 Channel3 Ouput Compare Refence clear bit */ TIM_ClearOC3Ref(TIM2, TIM_OCClear_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));

tmpccmr2 = TIMx->CCMR2;

/* Reset the OC3CE Bit */

tmpccmr2 &= CCMR_OC13CE_Reset;//0xFF7F, CCMR1.bit7//=1£¨Ò»µ©¼ì²âµ½ETRFÊäÈë¸ßµçƽ£¬Çå³ýOCxREF=0£©

/* Enable or Disable the Output Compare Clear Bit */ tmpccmr2 |= TIM_OCClear;

/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }

19.2.38 º¯ÊýTIM_ClearOC4Ref

Table 523. º¯ÊýTIM_ClearOC4Ref º¯ÊýÃû TIM_ClearOC4Ref º¯ÊýÔ­ÐÎ void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) ¹¦ÄÜÃèÊö ÔÚÒ»¸öÍⲿʼþ(ETRF¸ßµçƽ)ʱÇå³ý»ò±£³ÖOCREF4ÐźŠÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλ״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCClear£ºÊä³ö±È½ÏÇå³ýʹÄÜλµÄÖµÁоÙÈçÏÂ±í¡£ ¡¾TIM_ClearOC1Ref¡¿

TIM_OCClear ÃèÊö/CCMR1.bit7 #defineÖµ TIM_OCClear_Enable TIMxÊä³ö±È½ÏÇå³ýʹÄÜ 0x0080 TIM_OCClear_Disable TIMxÊä³ö±È½ÏÇå³ýʧÄÜ 0x0000 Àý£º

/* Enable the TIM2 Channel4 Ouput Compare Refence clear bit */ TIM_ClearOC4Ref(TIM2, TIM_OCClear_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, u16 TIM_OCClear) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));

tmpccmr2 = TIMx->CCMR2;

/* Reset the OC4CE Bit */

tmpccmr2 &= CCMR_OC24CE_Reset; //0x7FFF,CCMR2.bit15//=1£¨Ò»µ©¼ì²âµ½ETRFÊäÈë¸ßµçƽ£¬Çå³ýOCxREF=0£©

/* Enable or Disable the Output Compare Clear Bit */

tmpccmr2 |= (u16)(TIM_OCClear << 8); // CCMR2.OC2CE±ÈCCMR2.OC1CE¸ß8λ

/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }

19.2.39 º¯ÊýTIM_UpdateDisableConfig

Table 524. º¯ÊýTIM_UpdateDisableConfig º¯ÊýÃû TIM_UpdateDisableConfig void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, º¯ÊýÔ­ÐÎ FunctionalState Newstate) ¹¦ÄÜÃèÊö ʹÄÜ»òʧÄÜTIMx¸üÐÂʼþ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,6,7,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 NewState£ºTIMx_CR1¼Ä´æÆ÷UDISλµÄÐÂ״̬£¨ENABLE»òDISABLE£© Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ Àý£º /* Enables the Update event for TIM2 */ TIM_UpdateDisableConfig(TIM2, DISABLE); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) {

/* Check the parameters */

assert_param(IS_TIM_ALL_PERIPH(TIMx));

assert_param(IS_FUNCTIONAL_STATE(NewState));

if (NewState != DISABLE) {

/* Set the Update Disable Bit */

TIMx->CR1 |= CR1_UDIS_Set;// #define CR1_UDIS_Set ((u16)0x0002)//=1-½ûÖ¹¸üУ¬0-ÔÊÐí¸üР} else {

/* Reset the Update Disable Bit */

TIMx->CR1 &= CR1_UDIS_Reset;// #define CR1_UDIS_Reset ((u16)0x03FD)//bit15-10£¨6bit£©±£Áô } }

19.2.40 º¯ÊýTIM_EncoderInterfaceConfig

Table 525. º¯ÊýTIM_EncoderInterfaceConfig º¯ÊýÃû TIM_EncoderInterfaceConfig void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u8 TIM_EncoderMode, u8 TIM_IC1Polarity, u8 TIM_IC2Polarity) ¹¦ÄÜÃèÊö ÉèÖÃTIMx±àÂë½çÃæ£¨Ö»ÉèÖò»¿ªÆô£© ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_EncoderMode£º´¥·¢Ô´£¨±àÂ뷽ʽ£© ÊäÈë²ÎÊý3 TIM_ IC1Polarity£ºTI1¼«ÐÔ ÊäÈë²ÎÊý4 TIM_ IC2Polarity£ºTI2¼«ÐÔ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_EncoderMode£ºÑ¡ÔñTIMx±àÂëģʽ¡£ Table 526. TIM_EncoderModeÖµ ²ÎÊýTIM_EncoderModeÖµ ÃèÊö/SMCR.SMS[2:0] #defineÖµ ±¸×¢ TIM_EncoderMode_TI1 ʹÓÃTIM±àÂëģʽ1 0x0001 ¼ÆÊýÆ÷¸ù¾ÝTI1FP1µçƽÔÚTI2FP2µÄ±ßÑØ¼ÆÊý TIM_EncoderMode_TI1 ʹÓÃTIM±àÂëģʽ2 0x0002 ¼ÆÊýÆ÷¸ù¾ÝTI2FP2µçƽÔÚTI1FP1µÄ±ßÑØ¼ÆÊý º¯ÊýÔ­ÐÎ TIM_EncoderMode_TI12 ʹÓÃTIM±àÂëģʽ3 0x0003 ±ßÑØ¼ÆÊý TIM_ ICPolarity£ºÊäÈë²¶»ñ¼«ÐÔ ²ÎÊýTIM_ICxPolarityµÄÖµ ±íÊö/CCER.1/5/9/13 #defineÖµ ÒâÒå TIM_ICPolarity_Rising ÉÏÉýÑØ²¶»ñ£¨²»·´Ïࣩ ((u16)0x0000) ÊäÈë²¶»ñ TIM_ICPolarity_Falling ϽµÑز¶»ñ£¨·´Ïࣩ ((u16)0x0002) Àý£º ¼ÆÊýÆ÷¸ù¾ÝÁíÒ»ÐÅºÅµçÆ½ÔÚTI1FP1ºÍTI2FP2µÄ/* Configures the encoder mode TI1 for TIM2 */

TIM_EncoderInterfaceConfig(TIM2, TIM_EncoderMode_TI1, TIM_ICPolarity_Rising, TIM_ICPolarity_Rising); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode, u16 TIM_IC1Polarity,\\ u16 TIM_IC2Polarity) {

u16 tmpsmcr = 0; u16 tmpccmr1 = 0; u16 tmpccer = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));//±àÂ뷽ʽ1,2,3

assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));//ÊäÈë²¶»ñ·½Ê½£ºÉÏÉýÑØ£¿Ï½µÑØ£¿ assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));

/* Get the TIMx SMCR, CCMR1, CCER register value */ tmpsmcr = TIMx->SMCR; tmpccmr1 = TIMx->CCMR1; tmpccer = TIMx->CCER;

/* Set the encoder Mode */

tmpsmcr &= SMCR_SMS_Mask;// #define SMCR_SMS_Mask ((u16)0xFFF8) tmpsmcr |= TIM_EncoderMode;//¿´ÉÏÃæ¡¾±í526¡¿

/* Select the Capture Compare 1 and the Capture Compare 2 as input */

tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;// 0xFFFC 0xFCFF //CCyS-Ñ¡ÔñICyµÄÊäÈëÓ³É䷽ʽ tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set; // 0x0001 0x0100//ÉèÖÃΪֱͨӳÉäICy=TIy

/* Set the TI1,TI2 Polarities */

tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;// 0xFFFD 0xFFDF