STM32F10x - TIM - ͼÎÄ ÏÂÔØ±¾ÎÄ

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));

tmpccmr1 = TIMx->CCMR1;

/* Reset the OC2PE Bit */

tmpccmr1 &= CCMR_OC24PE_Reset;//bit11£¬0xF7FF

/* Enable or Disable the Output Compare Preload feature */

tmpccmr1 |= (u16)(TIM_OCPreload << 8);//CCMR1_OC2PE ±È CCMR1_OC1PE¸ß8λ

/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }

19.2.29 º¯ÊýTIM_OC3PreloadConfig

Table 512. º¯ÊýTIM_OC3PreloadConfig º¯ÊýÃû TIM_OC3PreloadConfig º¯ÊýÔ­ÐÎ void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) ¹¦ÄÜÃèÊö ʹÄÜ»òʧÄÜ TIMxÔÚCCR3ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_OCPreload£ºÊä³ö±È½ÏÔ¤×°ÔØ×´Ì¬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCPreload£ºÊä³ö±È½Ï Ô¤ÔØ×´Ì¬¡¾Í¬TIM_OC1PreloadConfig¡¿ ²ÎÊýTIM_OCPreloadÖµ ÃèÊö/CCMR1.OCyPE/bit3 #defineÖµ TIM_OCPreload_Enable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʹÄÜ 0x0008 TIM_OCPreload_Disable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʧÄÜ 0x0000 Àý£º

/* Enables the TIM2 Preload on CC3 Register */ TIM_OC3PreloadConfig(TIM2, TIM_OCPreload_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));

tmpccmr2 = TIMx->CCMR2;

/* Reset the OC3PE Bit */

tmpccmr2 &= CCMR_OC13PE_Reset;//0xFFF7,CCMR2

/* Enable or Disable the Output Compare Preload feature */ tmpccmr2 |= TIM_OCPreload;

/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }

19.2.30 º¯ÊýTIM_OC4PreloadConfig

Table 513. º¯ÊýTIM_OC4PreloadConfig º¯ÊýÃû TIM_OC4PreloadConfig º¯ÊýÔ­ÐÎ void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) ¹¦ÄÜÃèÊö ʹÄÜ»òÕßʧÄÜTIMxÔÚCCR4ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè TIM_OCPreload£ºÊä³ö±È½ÏÔ¤×°ÔØ×´Ì¬ ÊäÈë²ÎÊý2 ²ÎÔÄSection£ºTIM_OCPreload²éÔĸü¶à¸Ã²ÎÊýÔÊÐíȡֵ·¶Î§ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCPreload£ºÊä³ö±È½Ï Ô¤ÔØ×´Ì¬¡¾Í¬TIM_OC1PreloadConfig¡¿ ²ÎÊýTIM_OCPreloadÖµ ÃèÊö/CCMR1.OCyPE/bit3 TIM_OCPreload_Enable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʹÄÜ TIM_OCPreload_Disable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʧÄÜ Àý£º

/* Enables the TIM2 Preload on CC4 Register */ TIM_OC4PreloadConfig(TIM2, TIM_OCPreload_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));

tmpccmr2 = TIMx->CCMR2;

/* Reset the OC4PE Bit */

tmpccmr2 &= CCMR_OC24PE_Reset;//CCMR2,0xF7FF

/* Enable or Disable the Output Compare Preload feature */

tmpccmr2 |= (u16)(TIM_OCPreload << 8); //CCMR_OC4PE±È CCMR_OC3PE¸ß8λ

/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }

#defineÖµ 0x0008 0x0000 19.2.31 º¯ÊýTIM_OC1FastConfig

Table 514. º¯ÊýTIM_OC1FastConfig º¯ÊýÃû TIM_OC1FastConfig º¯ÊýÔ­ÐÎ void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) ¹¦ÄÜÃèÊö ÉèÖÃTIMx²¶»ñ±È½Ï1¿ìËÙÌØÕ÷ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCFast£ºÊä³ö±È½Ï¿ìËÙÌØÕ÷״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCFast :Êä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜ¿ÉÒÔʹÄÜ»òÕßʧÄÜ¡£ TIM_OCFast ÃèÊö #defineÖµ TIM_OCFast_Enable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʹÄÜ 0x0004 TIM_OCFast_Disable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʧÄÜ 0x0000 Àý£º

/* Use the TIM2 OC1 in fast Mode */

TIM_OC1FastConfig(TIM2, TIM_OCFast_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) {

u16 tmpccmr1 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));

/* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1;

/* Reset the OC1FE Bit */

tmpccmr1 &= CCMR_OC13FE_Reset;//0xFFFB£¬CCMR1.bit2// =1ʱ£¬OCFEÖ»ÔÚͨµÀ±»ÅäÖóÉPWM1»òPWM2ģʽʱÆð×÷ÓÃ

/* Enable or Disable the Output Compare Fast Bit */

tmpccmr1 |= TIM_OCFast;

/* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; }

19.2.32 º¯ÊýTIM_OC2FastConfig

Table 516. º¯ÊýTIM_OC2FastConfig º¯ÊýÃû TIM_OC2FastConfig º¯ÊýÔ­ÐÎ void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) ¹¦ÄÜÃèÊö ÉèÖÃTIMx²¶»ñ±È½Ï2¿ìËÙÌØÕ÷ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCFast£ºÊä³ö±È½Ï¿ìËÙÌØÕ÷״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCFast :Êä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜ¿ÉÒÔʹÄÜ»òÕßʧÄÜ¡£¡¾Í¬TIM_OC1FastConfig¡¿ TIM_OCFast ÃèÊö/CCMR1.OC1FE/bit2 #defineÖµ TIM_OCFast_Enable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʹÄÜ 0x0004 TIM_OCFast_Disable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʧÄÜ 0x0000 Àý£º

/* Use the TIM2 OC2 in fast Mode */

TIM_OC2FastConfig(TIM2, TIM_OCFast_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC2FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) {

u16 tmpccmr1 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));

/* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1;

/* Reset the OC2FE Bit */

tmpccmr1 &= CCMR_OC24FE_Reset;//CCMR1.bit10//0xFBFF// =1ʱ£¬OCFEÖ»ÔÚͨµÀ±»ÅäÖóÉPWM1»òPWM2ģʽʱÆð×÷ÓÃ

/* Enable or Disable the Output Compare Fast Bit */

tmpccmr1 |= (u16)(TIM_OCFast << 8);// CCMR1.OC2FE±ÈCCMR1.OC1FE¸ß8λ

/* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmr1; }

19.2.33 º¯ÊýTIM_OC3FastConfig

Table 517. º¯ÊýTIM_OC3FastConfig º¯ÊýÃû TIM_OC3FastConfig º¯ÊýÔ­ÐÎ void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) ¹¦ÄÜÃèÊö ÉèÖÃTIMx²¶»ñ±È½Ï3¿ìËÙÌØÕ÷ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCFast£ºÊä³ö±È½Ï¿ìËÙÌØÕ÷״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCFast :Êä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜ¿ÉÒÔʹÄÜ»òÕßʧÄÜ¡£¡¾Í¬TIM_OC1FastConfig¡¿ TIM_OCFast ÃèÊö/CCMR1.OC1FE/bit2 #defineÖµ TIM_OCFast_Enable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʹÄÜ 0x0004 TIM_OCFast_Disable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʧÄÜ 0x0000 Àý£º

/* Use the TIM2 OC3 in fast Mode */

TIM_OC3FastConfig(TIM2, TIM_OCFast_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC3FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));

/* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2;

/* Reset the OC3FE Bit */

tmpccmr2 &= CCMR_OC13FE_Reset;//0xFFFB£¬CCMR2.bit2 // =1ʱ£¬OCFEÖ»ÔÚͨµÀ±»ÅäÖóÉPWM1»òPWM2ģʽʱÆð×÷ÓÃ

/* Enable or Disable the Output Compare Fast Bit */ tmpccmr2 |= TIM_OCFast;

/* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; }

19.2.34 º¯ÊýTIM_OC4FastConfig

Table 518. º¯Êý TIM_OC4FastConfig º¯ÊýÃû TIM_OC4FastConfig º¯ÊýÔ­ÐÎ void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) ¹¦ÄÜÃèÊö ÉèÖÃTIMx²¶»ñ±È½Ï4¿ìËÙÌØÕ÷ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCFast£ºÊä³ö±È½Ï¿ìËÙÌØÕ÷״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCFast :Êä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜ¿ÉÒÔʹÄÜ»òÕßʧÄÜ¡£¡¾Í¬TIM_OC1FastConfig¡¿ TIM_OCFast ÃèÊö/CCMR1.OC1FE/bit2 #defineÖµ TIM_OCFast_Enable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʹÄÜ 0x0004 TIM_OCFast_Disable TIMxÊä³ö±È½Ï¿ìËÙÌØÕ÷ÐÔÄÜʧÄÜ 0x0000 Àý£º

/* Use the TIM2 OC4 in fast Mode */

TIM_OC4FastConfig(TIM2, TIM_OCFast_Enable); º¯ÊýÔ­ÐÍÈçÏ£º

void TIM_OC4FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast) {

u16 tmpccmr2 = 0;

/* Check the parameters */

assert_param(IS_TIM_123458_PERIPH(TIMx));

assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));

/* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2;

/* Reset the OC4FE Bit */

tmpccmr2 &= CCMR_OC24FE_Reset;//0xFBFF,CCMR2.bit10// =1ʱ£¬OCFEÖ»ÔÚͨµÀ±»ÅäÖóÉPWM1»òPWM2ģʽʱÆð×÷ÓÃ

/* Enable or Disable the Output Compare Fast Bit */

tmpccmr2 |= (u16)(TIM_OCFast << 8); // CCMR1.OC2FE±ÈCCMR1.OC1FE¸ß8λ

/* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmr2; }

19.2.35 º¯ÊýTIM_ClearOC1Ref

Table 519. º¯Êý TIM_ClearOC1Ref º¯ÊýÃû TIM_ClearOC1Ref