tmpccmr1 |= TIM_ForcedAction;
/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }
19.2.22 º¯ÊýTIM_ForcedOC2Config
Table 504. º¯ÊýTIM_ForcedOC2Config º¯ÊýÃû TIM_ForcedOC2Config º¯ÊýÔÐÎ void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) ¹¦ÄÜÃèÊö ÖÃTIMxÊä³ö2Ϊ»î¶¯»ò·Ç»î¶¯µçƽ ÊäÈë²ÎÊý1 TIMx£ºx¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_ForcedAction£ºÊä³öÐźŵÄÉèÖö¯×÷ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_ForcedAction£ºÊä³öÐźŵ͝×÷ÉèÖᣡ¾Í¬TIM_ForcedOC1Config¡¿ ²ÎÊýTIM_ForcedActionÖµ ÃèÊö/CCMR. OCyM[2:0]/bit #defineÖµ ±¸×¢ TIM_ForcedAction_Active ÖÃΪOCxREFÉϵĻµçƽ 0x0050 Ç¿ÖÆ¸ßµçƽ TIM_ForcedAction_InActive ÖÃΪOCxREFÉϵķǻµçƽ 0x0040 Ç¿ÖÆµÍµçƽ[ÎÞЧ] Àý£º
/* Forces the TIM2 Output Compare 2 signal to the active level */ TIM_ForcedOC2Config(TIM2, TIM_ForcedAction_Active); º¯ÊýÔÐÍÈçÏ£º
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) {
u16 tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC2M Bits */
tmpccmr1 &= CCMR_OC24M_Mask;//=0x8FFF,CCMR1
/* Configure The Forced output Mode */
tmpccmr1 |= (u16)(TIM_ForcedAction << 8);//OC2ÔÚOC1µÄ¸ß8λ´¦
/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }
19.2.23 º¯ÊýTIM_ForcedOC3Config
Table 505. º¯ÊýTIM_ForcedOC3Config º¯ÊýÃû TIM_ForcedOC3Config º¯ÊýÔÐÎ void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) ¹¦ÄÜÃèÊö ÖÃTIMxÊä³ö3Ϊ»î¶¯»ò·Ç»î¶¯µçƽ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_ForcedAction£ºÊä³öÐźŵÄÉèÖö¯×÷ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_ForcedAction£ºÊä³öÐźŵ͝×÷ÉèÖᣡ¾Í¬TIM_ForcedOC1Config¡¿ ²ÎÊýTIM_ForcedActionÖµ ÃèÊö/CCMR. OCyM[2:0]/bit #defineÖµ ±¸×¢ TIM_ForcedAction_Active ÖÃΪOCxREFÉϵĻµçƽ 0x0050 Ç¿ÖÆ¸ßµçƽ TIM_ForcedAction_InActive ÖÃΪOCxREFÉϵķǻµçƽ 0x0040 Ç¿ÖÆµÍµçƽ[ÎÞЧ] Àý£º
/* Forces the TIM2 Output Compare 3 signal to the active level */ TIM_ForcedOC3Config(TIM2, TIM_ForcedAction_Active); º¯ÊýÔÐÍÈçÏ£º
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) {
u16 tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr2 = TIMx->CCMR2;
/* Reset the OC1M Bits */
tmpccmr2 &= CCMR_OC13M_Mask;//CCMR2.bit6-4
/* Configure The Forced output Mode */
tmpccmr2 |= TIM_ForcedAction;//ÎÞЧµçƽ£¿¸ßµçƽ£¿
/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }
19.2.24 º¯ÊýTIM_ForcedOC4Config
Table 506. º¯Êý TIM_ForcedOC4Config º¯ÊýÃû TIM_ForcedOC4Config º¯ÊýÔÐÎ void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) ¹¦ÄÜÃèÊö ÖÃTIMxÊä³ö4Ϊ»î¶¯»ò·Ç»î¶¯µçƽ ÊäÈë²ÎÊý1 TIMx£ºx¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_ForcedAction£ºÊä³öÐźŵÄÉèÖö¯×÷ ²ÎÔÄSection£ºTIM_ForcedAction²éÔĸü¶à¸Ã²ÎÊýÔÊÐíȡֵ·¶Î§ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_ForcedAction£ºÊä³öÐźŵ͝×÷ÉèÖᣡ¾Í¬TIM_ForcedOC1Config¡¿ ²ÎÊýTIM_ForcedActionÖµ ÃèÊö/CCMR. OCyM[2:0]/bit #defineÖµ ±¸×¢ TIM_ForcedAction_Active ÖÃΪOCxREFÉϵĻµçƽ 0x0050 Ç¿ÖÆ¸ßµçƽ TIM_ForcedAction_InActive ÖÃΪOCxREFÉϵķǻµçƽ 0x0040 Ç¿ÖÆµÍµçƽ[ÎÞЧ] Àý£º /* Forces the TIM2 Output Compare 4 signal to the active level */ TIM_ForcedOC4Config(TIM2, TIM_ForcedAction_Active); º¯ÊýÔÐÍÈçÏ£º
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) {
u16 tmpccmr2 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); tmpccmr2 = TIMx->CCMR2;
/* Reset the OC2M Bits */
tmpccmr2 &= CCMR_OC24M_Mask;//0x8FFF,CCMR2
/* Configure The Forced output Mode */
tmpccmr2 |= (u16)(TIM_ForcedAction << 8);//OC4ÔÙOC3µÄ¸ß8λ´¦
/* Write to TIMx CCMR2 register */ TIMx->CCMR2 = tmpccmr2; }
19.2.25 º¯ÊýTIM_ARRPreloadConfig
Table 507. º¯ÊýTIM_ARRPreloadConfig º¯ÊýÃû TIM_ARRPreloadConfig º¯ÊýÔÐÎ ¹¦ÄÜÃèÊö ÊäÈë²ÎÊý 1 ÊäÈë²ÎÊý 2 Êä³ö²ÎÊý ·µ»ØÖµ ÏȾöÌõ¼þ ±»µ÷Óú¯Êý
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState Newstate) ʹÄÜ»òʧÄÜTIMxÔÚARRÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè NewState: TIM_CR1¼Ä´æÆ÷ARPEλµÄÐÂ״̬ ÎÞ ÎÞ ÎÞ ÎÞ Àý£º
/* Enables the TIM2 Preload on ARR Register */ TIM_ARRPreloadConfig(TIM2, ENABLE); º¯ÊýÔÐÍÈçÏ£º
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) {
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE) {
/* Set the ARR Preload Bit */
TIMx->CR1 |= CR1_ARPE_Set;//=0x0080 } else {
/* Reset the ARR Preload Bit */
TIMx->CR1 &= CR1_ARPE_Reset;//=0x037F(bit15-10±£Áô£¬±£³ÖΪ0) } }
19.2.26 º¯ÊýTIM_SelectCCDMA
Table 508. º¯ÊýTIM_SelectCCDMA º¯ÊýÃû TIM_SelectCCDMA º¯ÊýÔÐÎ void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState Newstate) ¹¦ÄÜÃèÊö Ñ¡ÔñTIMxÍâÉèµÄ²¶»ñ/±È½ÏDMAÔ´ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 NewState: ²¶»ñ±È½ÏDMAÔ´µÄÐÂ״̬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ Àý£º
/* Selects the TIM2 Capture Compare DMA source */ TIM_SelectCCDMA(TIM2, ENABLE); º¯ÊýÔÐÍÈçÏ£º
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) {
/* Check the parameters */
assert_param(IS_TIM_18_PERIPH(TIMx));//£¿£¿£¿T2-5¶¼ÓÐCR2 assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE) {
/* Set the COM Bit *///£¨ÈôCCUSÊÇÔ¤×°ÔØµÄ(CCPC=1)£¬¿ÉÒÔͨ¹ýÉèÖÃCOMλ»òTRGIÉϵÄÒ»¸öÉÏÉýÑØ¸üÐÂËüÃÇ£© TIMx->CR2 |= CR2_CCUS_Set; //#define CR2_CCUS_Set ((u16)0x0004)//CR2.bit3=CCUS } else {
/* Reset the COM Bit *///ÈôCCUSÊÇÔ¤×°ÔØµÄ(CCPC=1)£¬Ö»ÄÜͨ¹ýÉèÖÃCOMλ¸üÐÂËüÃÇ TIMx->CR2 &= CR2_CCUS_Reset; //#define CR2_CCUS_Reset ((u16)0xFFFB) } }
19.2.27 º¯ÊýTIM_OC1PreloadConfig
Table 509. º¯ÊýTIM_OC1PreloadConfig º¯ÊýÃû TIM_OC1PreloadConfig º¯ÊýÔÐÎ void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) ¹¦ÄÜÃèÊö ʹÄÜ»òʧÄÜTIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_OCPreload£ºÊä³ö±È½ÏÔ¤×°ÔØ×´Ì¬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCPreload £ºÊä³ö±È½ÏÔ¤×°ÔØ×´Ì¬¿ÉÒÔʹÄÜ»òÕßʧÄÜÈçÏÂ±í¡£ Table 510. TIM_OCPreloadÖµ ²ÎÊýTIM_OCPreloadÖµ ÃèÊö/CCMR1.OCyPE/bit3 #defineÖµ TIM_OCPreload_Enable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʹÄÜ 0x0008 TIM_OCPreload_Disable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʧÄÜ 0x0000 Àý£º
/* Enables the TIM2 Preload on CC1 Register */
TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Enable); º¯ÊýÔÐÍÈçÏ£º
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) {
u16 tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1PE Bit */
tmpccmr1 &= CCMR_OC13PE_Reset;//0xFFF7,bit3
/* Enable or Disable the Output Compare Preload feature */ tmpccmr1 |= TIM_OCPreload;
/* Write to TIMx CCMR1 register */ TIMx->CCMR1 = tmpccmr1; }
19.2.28 º¯ÊýTIM_OC2PreloadConfig
Table 511. º¯ÊýTIM_OC2PreloadConfig º¯ÊýÃû TIM_OC2PreloadConfig º¯ÊýÔÐÎ void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) ¹¦ÄÜÃèÊö ʹÄÜ»òʧÄÜTIMxÔÚCCR2ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_OCPreload£ºÊä³ö±È½Ï Ô¤ÔØ×´Ì¬ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_OCPreload£ºÊä³ö±È½Ï Ô¤ÔØ×´Ì¬¡¾Í¬TIM_OC1PreloadConfig¡¿ ²ÎÊýTIM_OCPreloadÖµ ÃèÊö/CCMR1.OCyPE/bit3 #defineÖµ TIM_OCPreload_Enable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʹÄÜ 0x0008 TIM_OCPreload_Disable TIMxÔÚCCR1ÉϵÄÔ¤×°ÔØ¼Ä´æÆ÷ʧÄÜ 0x0000 Àý£º /* Enables the TIM2 Preload on CC2 Register */ TIM_OC2PreloadConfig(TIM2, TIM_OCPreload_Enable); º¯ÊýÔÐÍÈçÏ£º
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, u16 TIM_OCPreload) {
u16 tmpccmr1 = 0;