º¯ÊýÃû º¯ÊýÔÐÎ ¹¦ÄÜÃèÊö ÊäÈë²ÎÊý1 ÊäÈë²ÎÊý2 ÊäÈë²ÎÊý3 ÊäÈë²ÎÊý4 Êä³ö²ÎÊý ·µ»ØÖµ ÏȾöÌõ¼þ ±»µ÷Óú¯Êý TIM_ETRClockMode2Config void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter) ÅäÖÃTIMxÍⲿʱÖÓģʽ2 TIMx£ºx¿ÉÒÔÊÇ1,2,3,4,5,8£¬À´Ñ¡ÔñTIMÍâÉè TIM_ExtTRGPrescaler£ºÍⲿ´¥·¢Ô¤·ÖƵ TIM_ExtTRGPolarity£ºÍⲿʱÖÓ¼«ÐÔ ExtTRGFilter£ºÍⲿ´¥·¢Â˲¨Æ÷¡£È¡ÖµÔÚ0x0-0xFÖ®¼ä¡£ ÎÞ ÎÞ ÎÞ ÎÞ Àý£º /* Selects the external clock Mode 2 for TIM2: the external clock is connected to ETR input pin, the rising edge is the active edge, no filter sampling is done (ExtTRGFilter = 0) and the prescaler is fixed to TIM_ExtTRGPSC_DIV2 */
TIM_ExternalCLK2Config(TIM2, TIM_ExtTRGPSC_DIV2, TIM_ExtTRGPolarity_NonInverted, 0x0); º¯ÊýÔÐÍÈçÏ£º
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter) {
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));//¹Ø£»/2£»/4£»/8
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));//0x8000£¨·×ª£©£»0x0000£¨²»£© assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
/* Configure the ETR Clock source */
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);//ÍⲿʱÖÓÉèÖ㨹²Èý¸ö£©
/* Enable the External clock mode2 */
TIMx->SMCR |= SMCR_ECE_Set;//ÍⲿʱÖÓʹÄÜ£ºSMCR.bit14 [ECE] }
/*
void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter) {
u16 tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
tmpsmcr = TIMx->SMCR;
/* Reset the ETR Bits */
tmpsmcr &= SMCR_ETR_Mask;// #define SMCR_ETR_Mask ((u16)0x00FF)
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8);// bit13-12 | bit15 | bit11-8<=0xF
/* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } */
19.2.17 º¯ÊýTIM_ETRConfig
Table 496. º¯ÊýTIM_ETRConfig º¯ÊýÃû TIM_ETRConfig void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, º¯ÊýÔÐÎ u16 TIM_ExtTRGPolarity, u8 ExtTRGFilter) ¹¦ÄÜÃèÊö ÅäÖÃTIMxÍⲿ´¥·¢ ÊäÈë²ÎÊý 1 TIMx£ºx¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_ExtTRGPrescaler£ºÍⲿ´¥·¢Ô¤·ÖƵ ÊäÈë²ÎÊý 3 TIM_ExtTRGPolarity£ºÍⲿʱÖÓ¼«ÐÔ ÊäÈë²ÎÊý 4 ExtTRGFilter£ºÍⲿ´¥·¢Â˲¨Æ÷¡£È¡ÖµÔÚ0x0-0xFÖ®¼ä¡£ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ Àý£º
/* Configure the External Trigger (ETR) for TIM2: the rising edge is the active edge, no filter sampling is done (ExtTRGFilter = 0) and the prescaler is fixed to TIM_ExtTRGPSC_DIV2 */
TIM_ExternalCLK2Config(TIM2, TIM_ExtTRGPSC_DIV2, TIM_ExtTRGPolarity_NonInverted, 0x0); º¯ÊýÔÐÍÈçÏ£º
void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter) {
u16 tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));//¹Ø±Õ£¬1/2£»1/4£»1/8¡£ assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));//bit 15 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); //<=0xF
tmpsmcr = TIMx->SMCR;
/* Reset the ETR Bits */
tmpsmcr &= SMCR_ETR_Mask;// #define SMCR_ETR_Mask ((u16)0x00FF)//Çå³ýËùÓÐETRÉèÖá£
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8); // bit13-12 | bit15 | bit11-8<0xF
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;//ÉèÖõ«²»Ê¹ÄÜ¡£ }
19.2.18 º¯ÊýTIM_SelectInputTrigger
Table 497. º¯ÊýTIM_SelectInputTrigger º¯ÊýÃû TIM_SelectInputTrigger º¯ÊýÔÐÎ void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) ¹¦ÄÜÃèÊö Ñ¡ÔñTIMxÊäÈë´¥·¢Ô´ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_InputTriggerSource£ºÊäÈë´¥·¢Ô´ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_InputTriggerSource £ºÑ¡ÔñTIMxÊäÈë´¥·¢Ô´¡£¼ûTable 498. ²ÎÔĸòÎÊýµÄȡֵ¡£ Table 498. TIM_InputTriggerSourceÖµ TIM_InputTriggerSource ÃèÊö/SMCR. TS[2:0]/bit6-4 #defineÖµ TIM_TS_ITR0 TIMÄÚ²¿´¥·¢0 0x0000 TIM_TS_ITR1 TIMÄÚ²¿´¥·¢1 0x0010 TIM_TS_ITR2 TIMÄÚ²¿´¥·¢2 0x0020 TIM_TS_ITR3 TIMÄÚ²¿´¥·¢3 0x0030 TIM_TS_TI1F_ED TIM TL1±ßÑØÌ½²âÆ÷ 0x0040 TIM_TS_TI1FP1 TIM¾Â˲¨¶¨Ê±Æ÷ÊäÈë1 0x0050 TIM_TS_TI2FP2 TIM¾Â˲¨¶¨Ê±Æ÷ÊäÈë2 0x0060 TIM_TS_ETRF TIMÍⲿ´¥·¢ÊäÈë 0x0070 Àý£º /* Selects the Internal Trigger 3 as input trigger fot TIM2 */ void TIM_SelectInputTrigger(TIM2, TIM_TS_ITR3); º¯ÊýÔÐÍÈçÏ£º
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource) {
u16 tmpsmcr = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
/* Reset the TS Bits */
tmpsmcr &= SMCR_TS_Mask;//£¨u16£©0xFF8F
/* Set the Input Trigger source */ tmpsmcr |= TIM_InputTriggerSource;
/* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; }
19.2.19 º¯ÊýTIM_PrescalerConfig
Table 499. º¯ÊýTIM_PrescalerConfig //ΪCNT¹¤×÷×ö×¼±¸ º¯ÊýÃû TIM_PrescalerConfig void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, º¯ÊýÔÐÎ u16 TIM_PSCReloadMode) ¹¦ÄÜÃèÊö ÉèÖÃTIMxÔ¤·ÖƵ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 CNTµÄǰ Ô¤·ÖƵֵ£¨0x0000-0xFFFF£©¡¾CK_PSC?CK_CNT¡¿ ÊäÈë²ÎÊý3 TIM_PSCReloadMode£ºÔ¤·ÖÆµÖØÔØÄ£Ê½ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_PSCReloadMode£ºÑ¡ÔñÔ¤·ÖÆµÖØÔØÄ£Ê½¡£¼ûTable 500. ²ÎÔĸòÎÊýµÄȡֵ¡£ Table 500. TIM_PSCReloadModeÖµ TIM_PSCReloadMode ÃèÊö/EGR.bit0/UG #defineÖµ TIM_PSCReloadMode_Update TIMÔ¤·ÖƵֵÔÚ¸üÐÂʼþʱװÈë 0x0000 TIM_PSCReloadMode_Immediate TIMÔ¤·ÖƵֵ¼´Ê±×°Èë 0x0001 Àý£º /* Configures the TIM2 new Prescaler value */ u16 TIMPrescaler = 0xFF00;
TIM_PrescalerConfig(TIM2, TIMPrescaler, TIM_PSCReloadMode_Immediate); º¯ÊýÔÐÍÈçÏ£º
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, u16 Prescaler, u16 TIM_PSCReloadMode) {
/* Check the parameters */
assert_param(IS_TIM_ALL_PERIPH(TIMx));
assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
/* Set the Prescaler value */
TIMx->PSC = Prescaler;//fCK_CNT=fCK_PSC/(PSC[15:0]+1)
/* Set or reset the UG Bit */ TIMx->EGR = TIM_PSCReloadMode;
//´ËÓï¾ä²»ÊÇ×î¼Ñ·½Ê½£º°ÑTIM_PSCReloadMode_UpdateµÄÖµ¸ÄΪOxFFFE£¬È»ºóÓÃÌõ¼þÀ´&»ò|£¬±ÜÃâ¸ü¸ÄEGRµÄÆäËûλ¡£ }
19.2.20 º¯ÊýTIM_CounterModeConfig
Table 501. º¯ÊýTIM_CounterModeConfig º¯ÊýÃû TIM_CounterModeConfig º¯ÊýÔÐÎ void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) ¹¦ÄÜÃèÊö ÉèÖÃTIMx¼ÆÊýÆ÷ģʽ ÊäÈë²ÎÊý1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý2 TIM_CounterMode£º´ýʹÓõļÆÊýÆ÷ģʽ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_CounterMode£º´ýʹÓõļÆÊýÆ÷ģʽ¡£
²ÎÊýTIM_CounterModeµÄÖµ TIM_CounterMode_Up TIM_CounterMode_Down ÃèÊö/CR1. CMS[1:0] +DIR/bit6-5+bit4 ÏòÉϼÆÊý ÏòϼÆÊý #defineÖµ ((u16)0x0000) ((u16)0x0010) CMS[1:0]ÖÐÑë¼ÆÊý·½Ïò ¶ÔÆëģʽѡÔñ bit6-5=00 [±ßÔµ¶ÔÆë] bit4=0 bit4=1 bit4=0 ¶ÔCMSÎÞЧ TIM_CounterMode_CenterAligned1 ÖÐÑë¶ÔÆëģʽ1 TIM_CounterMode_CenterAligned2 ÖÐÑë¶ÔÆëģʽ1 TIM_CounterMode_CenterAligned3 ÖÐÑë¶ÔÆëģʽ1 ((u16)0x0020) bit6-5=01 ((u16)0x0040) bit6-5=10 ((u16)0x0060) bit6-5=11 Àý£º
/* Selects the Center Aligned counter Mode 1 for the TIM2 */ TIM_CounterModeConfig(TIM2, TIM_Counter_CenterAligned1); º¯ÊýÔÐÍÈçÏ£º
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, u16 TIM_CounterMode) {
u16 tmpcr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
tmpcr1 = TIMx->CR1;
/* Reset the CMS and DIR Bits */
tmpcr1 &= CR1_CounterMode_Mask;//0xFF8F=bit6-5+bit4
/* Set the Counter Mode */ tmpcr1 |= TIM_CounterMode;
/* Write to TIMx CR1 register */ TIMx->CR1 = tmpcr1; }
19.2.21 º¯ÊýTIM_ForcedOC1Config
Table 502. º¯Êý TIM_ForcedOC1Config º¯ÊýÃû TIM_ForcedOC1Config º¯ÊýÔÐÎ void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) ¹¦ÄÜÃèÊö ÖÃTIMxÊä³ö1Ϊ»î¶¯»ò·Ç»î¶¯µçƽ ÊäÈë²ÎÊý 1 TIMx£ºx ¿ÉÒÔÊÇ1,2,3,4,5,8À´Ñ¡ÔñTIMÍâÉè ÊäÈë²ÎÊý 2 TIM_ForcedAction£ºÊä³öÐźŵÄÉèÖö¯×÷ Êä³ö²ÎÊý ÎÞ ·µ»ØÖµ ÎÞ ÏȾöÌõ¼þ ÎÞ ±»µ÷Óú¯Êý ÎÞ TIM_ForcedAction £ºÊä³öÐźŵÄÉèÖö¯×÷ȡֵ¼ûÏÂ±í¡£ Table 503. TIM_ForcedActionÖµ ²ÎÊýTIM_ForcedActionÖµ ÃèÊö/CCMR. OCyM[2:0]/bit #defineÖµ ±¸×¢ TIM_ForcedAction_Active ÖÃΪOCxREFÉϵĻµçƽ 0x0050 Ç¿ÖÆ¸ßµçƽ TIM_ForcedAction_InActive ÖÃΪOCxREFÉϵķǻµçƽ 0x0040 Ç¿ÖÆµÍµçƽ[ÎÞЧ] Àý£º /* Forces the TIM2 Output Compare 1 signal to the active level */ TIM_ForcedOC1Config(TIM2, TIM_ForcedAction_Active); º¯ÊýÔÐÍÈçÏ£º
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction) {
u16 tmpccmr1 = 0;
/* Check the parameters */
assert_param(IS_TIM_123458_PERIPH(TIMx));
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
tmpccmr1 = TIMx->CCMR1;
/* Reset the OC1M Bits */
tmpccmr1 &= CCMR_OC13M_Mask;//OxFF8F,bit6-4 = CCMR1.OC1M[2:0]
/* Configure The Forced output Mode */