#include #include #define INT8U unsigned char #define INT16U unsigned int #define WRITE_BURST 0x40 //Á¬ÐøдÈë #define READ_SINGLE 0x80 //¶Á #define READ_BURST 0xC0 //Á¬Ðø¶Á #define BYTES_IN_RXFIFO 0x7F //½ÓÊÕ»º³åÇøµÄÓÐЧ×Ö½ÚÊý

#define CRC_OK 0x80 //CRCУÑéͨ¹ýλ±êÖ¾ //***************************************************************************************** sbit CSN =P2^0; sbit GDO0 =P2^1; sbit GDO2 =P2^3; sbit MISO =P2^4; sbit SCK =P2^5; sbit MOSI =P2^6;

//*****************************************************************************************

//***************************************************************************************** sbit led0=P0^0; sbit led1=P0^1; sbit led2=P0^2;

//*****************************************************************************************

//INT8U PaTabel[8] = {0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60 ,0x60};

//***************************************************************************************** void SpiInit(void); void CpuInit(void);

void RESET_CC1100(void);

void POWER_UP_RESET_CC1100(void);

void halSpiWriteReg(INT8U addr, INT8U value);

void halSpiWriteBurstReg(INT8U addr, INT8U *buffer, INT8U count); void halSpiStrobe(INT8U strobe); INT8U halSpiReadReg(INT8U addr);

void halSpiReadBurstReg(INT8U addr, INT8U *buffer, INT8U count); INT8U halSpiReadStatus(INT8U addr); void halRfWriteRfSettings(void);

void halRfSendPacket(INT8U *txBuffer, INT8U size);

INT8U halRfReceivePacket(INT8U *rxBuffer, INT8U *length);

//*****************************************************************************************

// CC1100 STROBE, CONTROL AND STATUS REGSITER

#define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds #define CCxxx0_SYNC1 0x04 // Sync word, high INT8U #define CCxxx0_SYNC0 #define CCxxx0_PKTLEN #define CCxxx0_PKTCTRL1 #define CCxxx0_PKTCTRL0 #define CCxxx0_ADDR #define CCxxx0_CHANNR #define CCxxx0_FSCTRL1 #define CCxxx0_FSCTRL0 #define CCxxx0_FREQ2 #define CCxxx0_FREQ1 #define CCxxx0_FREQ0 #define CCxxx0_MDMCFG4 #define CCxxx0_MDMCFG3 #define CCxxx0_MDMCFG2 #define CCxxx0_MDMCFG1 #define CCxxx0_MDMCFG0 #define CCxxx0_DEVIATN #define CCxxx0_MCSM2 configuration

#define CCxxx0_MCSM1 configuration

#define CCxxx0_MCSM0 configuration

#define CCxxx0_FOCCFG #define CCxxx0_BSCFG #define CCxxx0_AGCCTRL2 #define CCxxx0_AGCCTRL1 #define CCxxx0_AGCCTRL0 #define CCxxx0_WOREVT1 #define CCxxx0_WOREVT0 #define CCxxx0_WORCTRL #define CCxxx0_FREND1 #define CCxxx0_FREND0 #define CCxxx0_FSCAL3 #define CCxxx0_FSCAL2 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 // Sync word, low INT8U // Packet length

// Packet automation control // Packet automation control // Device address // Channel number

// Frequency synthesizer control // Frequency synthesizer control

// Frequency control word, high INT8U // Frequency control word, middle INT8U // Frequency control word, low INT8U // Modem configuration // Modem configuration // Modem configuration // Modem configuration // Modem configuration // Modem deviation setting

// Main Radio Control State Machine // Main Radio Control State Machine // Main Radio Control State Machine // Frequency Offset Compensation configuration // Bit Synchronization configuration // AGC control // AGC control // AGC control

// High INT8U Event 0 timeout // Low INT8U Event 0 timeout // Wake On Radio control // Front end RX configuration // Front end TX configuration

// Frequency synthesizer calibration // Frequency synthesizer calibration

#define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration

#define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control #define CCxxx0_PTEST 0x2A // Production test #define CCxxx0_AGCTEST 0x2B // AGC test

#define CCxxx0_TEST2 0x2C // Various test settings #define CCxxx0_TEST1 0x2D // Various test settings #define CCxxx0_TEST0 // Strobe commands

#define CCxxx0_SRES #define CCxxx0_SFSTXON MCSM0.FS_AUTOCAL=1).

synthesizer is

#define CCxxx0_SXOFF #define CCxxx0_SCAL #define CCxxx0_SRX from IDLE and

#define CCxxx0_STX first if

CCA is enabled:

#define CCxxx0_SIDLE exit

#define CCxxx0_SAFC synthesizer

#define CCxxx0_SWOR (Wake-on-Radio)

#define CCxxx0_SPWD #define CCxxx0_SFRX #define CCxxx0_SFTX #define CCxxx0_SWORRST #define CCxxx0_SNOP commands to two

#define CCxxx0_PARTNUM #define CCxxx0_VERSION 0x2E 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x30 0x31

// Various test settings // Reset chip.

// Enable and calibrate frequency synthesizer (if // If in RX/TX: Go to a wait state where only the // running (for quick RX / TX turnaround). // Turn off crystal oscillator.

// Calibrate frequency synthesizer and turn it off // (enables quick start).

// Enable RX. Perform calibration first if coming // MCSM0.FS_AUTOCAL=1.

// In IDLE state: Enable TX. Perform calibration // MCSM0.FS_AUTOCAL=1. If in RX state and // Only go to TX if channel is clear.

// Exit RX / TX, turn off frequency synthesizer and // Wake-On-Radio mode if applicable.

// Perform AFC adjustment of the frequency // Start automatic RX polling sequence // Enter power down mode when CSn goes high. // Flush the RX FIFO buffer. // Flush the TX FIFO buffer. // Reset real time clock.

// No operation. May be used to pad strobe // INT8Us for simpler software. #define CCxxx0_FREQEST 0x32 #define CCxxx0_LQI 0x33 #define CCxxx0_RSSI 0x34 #define CCxxx0_MARCSTATE 0x35 #define CCxxx0_WORTIME1 0x36 #define CCxxx0_WORTIME0 0x37 #define CCxxx0_PKTSTATUS 0x38 #define CCxxx0_VCO_VC_DAC 0x39 #define CCxxx0_TXBYTES 0x3A #define CCxxx0_RXBYTES 0x3B #define CCxxx0_PATABLE 0x3E #define CCxxx0_TXFIFO 0x3F #define CCxxx0_RXFIFO 0x3F

// RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers typedef struct S_RF_SETTINGS {

INT8U FSCTRL2; //×ÔÒѼӵÄ

INT8U FSCTRL1; // Frequency synthesizer control. INT8U FSCTRL0; // Frequency synthesizer control.

INT8U FREQ2; // Frequency control word, high INT8U. INT8U FREQ1; // Frequency control word, middle INT8U. INT8U FREQ0; // Frequency control word, low INT8U. INT8U MDMCFG4; // Modem configuration. INT8U MDMCFG3; // Modem configuration. INT8U MDMCFG2; // Modem configuration. INT8U MDMCFG1; // Modem configuration. INT8U MDMCFG0; // Modem configuration. INT8U CHANNR; // Channel number.

INT8U DEVIATN; // Modem deviation setting (when FSK modulation is enabled). INT8U FREND1; // Front end RX configuration. INT8U FREND0; // Front end RX configuration.

INT8U MCSM0; // Main Radio Control State Machine configuration. INT8U FOCCFG; // Frequency Offset Compensation Configuration. INT8U BSCFG; // Bit synchronization Configuration. INT8U AGCCTRL2; // AGC control. INT8U AGCCTRL1; // AGC control. INT8U AGCCTRL0; // AGC control.

INT8U FSCAL3; // Frequency synthesizer calibration. INT8U FSCAL2; // Frequency synthesizer calibration. INT8U FSCAL1; // Frequency synthesizer calibration. INT8U FSCAL0; // Frequency synthesizer calibration.

INT8U FSTEST; // Frequency synthesizer calibration control INT8U TEST2; // Various test settings. INT8U TEST1; // Various test settings.