范明轲 0958200102 南京理工大学 2012 – 03 – 26
10. 选择模块：有三个模式：
1． 计 星期：小时：分：秒 2． 设闹钟时间 3． 计 年：月：日
用六个数据选择器：
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
11. 显示模块：采用动态显示方法，其动态扫描频率为1MHz。显示模块包括一个6选1
数据选择器(其从计数模块输出的6个输出选1个送出显示)和一个译码器(其对6选1数据选择器的输出信号进行译码送至数码管上显示)。用VHDL硬件语言实现即程序代码如下：
(1) 6选1数据选择器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY sel IS PORT( clk: IN STD_LOGIC; rst: IN STD_LOGIC; qin1: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin3: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin4: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin5: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin6: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin7: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin8: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qout: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); sel: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END sel;
ARCHITECTURE behav OF sel IS BEGIN PROCESS(clk,rst) VARIABLE cnt: INTEGER RANGE 0 TO 5; BEGIN IF(rst='0') THEN cnt:=0; sel<=\ qout<=\ ELSIF (clk'event AND clk='1') THEN IF(cnt=5)THEN cnt:=0; ELSE cnt:=cnt+1; END IF; CASE cnt IS WHEN 0=>qout<=qin1; sel<=\ WHEN 1=>qout<=qin2; sel<=\
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
WHEN 2=>qout<=qin3; sel<=\ WHEN 3=>qout<=qin4; sel<=\ WHEN 4=>qout<=qin5; sel<=\ WHEN 5=>qout<=qin6; sel<=\ WHEN 6=>qout<=qin7; sel<=\ WHEN 7=>qout<=qin8; sel<=\ WHEN others=>qout<=\ sel<=\ END CASE; END IF; END PROCESS; END behav;
仿真波形：例如显示04：21:52:40其从仿真波形结果可看知所设计的是正确的。
其封装图为：
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
(2) 4-7译码器：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY decode47 IS
PORT( qin: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qout: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decode47;
ARCHITECTURE behav OF decode47 IS BEGIN
WITH qin SELECT
qout<=\ \ \ \ \ \ \ \ \ \ \END behav;
其封装图为：
decode47qin[3..0]qout[7..0]inst 12. 报时模块：由设计要求电子钟在每小时到来前进行报时：59:53, 55:55，59:57 鸣
叫频率为1kHz；59:59鸣叫频率为2kHz，从而可以很容易采用VHDL语言编写程序实现，代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY bell IS
PORT( clk_1k: IN STD_LOGIC; clk_2k: IN STD_LOGIC;
qin1: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin2: IN STD_LOGIC_VECTOR(3 DOWNTO 0); qin3: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
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