范明轲 0958200102 南京理工大学 2012 – 03 – 26
END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF; END IF;
END IF; END IF; END IF; END IF; END IF;
qout1<=tem1; qout2<=tem2; END PROCESS; END behav; 仿真
1， 在瑞年 1984/02
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
普通年
模块
6. 计月模块： 模12的计数，VHDL程序如下
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY yue IS
PORT( clk: IN STD_LOGIC; rst: IN STD_LOGIC; en: IN STD_LOGIC;
qout1: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); qout2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
co: OUT STD_LOGIC);
END yue;
ARCHITECTURE behav OF yue IS
SIGNAL tem1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL tem2: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(clk,rst) BEGIN IF (en='1')THEN tem1<=tem1;
tem2<=tem2;
ELSIF(rst='0')THEN tem1<=\
tem2<=\
ELSIF(clk'event AND clk='1')THEN IF (tem2=\ tem1<=\ tem2<=\
co<='1';
ELSE co<='0';
IF(tem1=\
tem1<=\
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范明轲 0958200102 南京理工大学 2012 – 03 – 26
tem2<=tem2+1; ELSE
tem1<=tem1+1;
END IF;
END IF;
END IF; qout1<=tem1; qout2<=tem2;
END PROCESS;
END behav; 仿真：
模块
7. 计年模块： 模12的计数，VHDL程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY nian IS
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